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Trying to read ADS1256 register's values

FL53381
Prodigy 30 points
Other Parts Discussed in Thread: ADS1256

Hi,

I'm trying to read the ADS1256 register's values - which seem not the correct values that I got. Could you help to look into it?

 

Thanks,

Feng

  • 0
    TI__Guru* 97825 points

    As a quick answer, I can think of two things to try.

    First, before reading the registers, send an SDATAC (03) command. This will prevent the DOUT from being updated with data at every DRDY pulse. It could be that the register read is being corrupted by data being sent to DOUT.

    Second, during the read of the register, I would do this with a single CSn low. So, bring CSn low, and issue 10 0B FF ... FF and then bring CSn high again.

    If none of this helps, you can repost here.


    Joseph Wu

  • 0 in reply to Joseph Wu
    TI__Guru* 97825 points

    One other thing to check (brought up by my colleague Tom Hendrick) is the phase of the read and write.

    The data is read out and clocked in on the falling edge of SCLK. From your second picture, it looks like you have data clocking in on the rising edge of SCLK.


    Joseph Wu


    (Thanks Tom)

  • 0 in reply to Joseph Wu
    Prodigy 30 points

    Thank you guys for the help!

    I do select  falling edge of SCLK when I set up SPI bus clock(FYI - I'm using Freescale MCU, MCF51JM connect to ADS1256EVM Board)).

    Now it seems better after following your suggestions -  bring CSn low, issue SDATAC (0x0F) command and then issue 10 0B FF ... FF and then bring CSn high again. The read out data from registers seems more reliable, but not sure there are correct values... Here is what I've got form DOUT:  0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

    For read data from the MUX AIN0, AIN1, it seems the value is not reliable. Here is my pseudo code:

    Bring CSn low, issue SYNC command(0xFC); delay 6 us; issue WAKEUP command(0xFF); wait about 6 us; wait until DRDY low; issue RDATA command(0x01); delay 6 us; read data from DOUT (24bit); then bring CSn high again. I did not send WREG command, since I'm only interesting AIN0 and AIN1 input, could that be issue?

     

  • 0 in reply to FL53381
    TI__Guru* 97825 points

    I would check your communications again. From your second scope photo, it looks like your DIN is being setup on the falling edge of SCLK for the ADS1256 to be latched in on the rising edge of SCLK.

    Second, the reset or default values for the register are given in Table 23 of the ADS1256 datasheet (third column). I'm not sure of all values but depending on the device, they are:

    ADD   Default Value

    00h    x1h

    01h    01h

    02h    20h

    03h    F0h

    04h    E0h

    05h    xxh  (probably 00h)

    06h    xxh  (probably 00h)

    ....


    Joseph Wu

  • 0 in reply to Joseph Wu
    Prodigy 30 points

    Thank you Joseph, everything works now, and repeatable at 1.714MHz shift clock rate!

    One of the main issue was selecting the falling edge of SCLK at the SPI initial settings. I have to change it to rising edge of SCLK again.

    Appreciate your help, great work!

     

    Feng