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DAC5682Z serial interface readout problem

lev aleshin
Prodigy 10 points

Other Parts Discussed in Thread: DAC5682Z

Hi i am starting working with 5682, and have invalid serial readout from registers(massive deviation from default states when i read).

Writhig to registers also did not affect reading values.

Writing config6 sleep bits separetly looks like reducing supply current correctly.

Also i cant get any signal from DAC output. (both outs coupled with 1k resistors and both have low voltage).

3v3 current 121mA, 1v8 current 58mA. (clkin 35Mhz, no initialisation, no data feed, LVDS N-pins on 1.2v, P-pins disconnected);

What can be wrong?

Lev

  • 0
    TI__Guru* 91947 points

    Lev,

    We are looking into this.

    Regards,

    Jim

  • 0 in reply to jim s
    TI__Mastermind 20541 points
    Hi Lev,

    Have you been following the initialization set up for the device as mentioned on page 55 the datasheet also shown below?

    The following start-up sequence is recommended to initialize the DAC5682Z:
    1. Supply all 1.8 V (CLKVDD, DVDD, VFUSE) voltages simultaneously followed by all 3.3 V (AVDD and
    IOVDD) voltages.
    2. Provide stable CLKIN/C clock.
    3. Toggle RESETB pin for a minimum 25 nSec active low pulse width.
    4. Program all desired SIF registers. Set DLL_Restart bit during this write cycle. The CONFIG10 register value
    should match the corresponding DCLKP/N frequency range in the Electrical Characteristics table.
    5. Provide stable DCLKP/N clock. (This can also be provided earlier in the sequence)
    6. Clear the DLL_Restart bit when the DCLKP/N clock is expected to be stable.
    7. Verify the status of DLL_Lock and repeat until set to ‘1’. DLL_Lock can be monitored by reading the
    STATUS0 register or by monitoring the SDO pin in 3-wire SIF mode. (See description for CONFIG14
    SDO_func_sel.)
    8. Enable transmit of data by asserting the LVDS SYNCP/N input or setting CONFIG3 SW_sync bit. (See
    description for CONFIG3 SW_sync and SW_sync_sel) The SYNC source must be held at a logic ‘1’ to
    enable data flow through the DAC. If multiple DAC devices require synchronization, refer to the
    "Recommended Multi-DAC Synchronization Procedure" below.
    9. Provide data flow to LVDS D[15:0]P/N pins. If using the LVDS SYNCP/N input, data can be input
    simultaneous with the logic ‘1’ transition of SYNCP/N.

    Regards,
    Neeraj Gill