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THS8200 Register settings for HD video

Other Parts Discussed in Thread: THS8200

Now our company use your THS8200  and meet problems about registers setting . Hope your help!

Please tell me the ths8200 setting for VGA output of 1024*768 @60p,1024*768 @75p,1280*1024@60p.

And ths8200 settting for YPbPr output of 1280*720@50p,1280*720@60p,1920*1080@25p,1920*1080@50i,1920*1080@30p,1920*1080@60i,

  • Xiaoyu,

    Thanks for your interest in the THS8200.  We'll respond to your question as soon as possible.

    Regards,

    Jim

  • Xiaoyu,

    Below are the addtionial graphics settings.  All that changes for the various graphics formats is pixels per line, line per frame, HSOUT width, VSOUT width, and HS/VSout polarity.

    Regarding the HD settings, what type of interface will you be using?  Will it be like the graphics interface but with 24-bit YCbCr and discrete syncs?

    Regards,

    Larry

     

    //"THS8200_800x600x60Hz - 40MHz DE Blanking Enabled HS/VS+/+"
    //DE operation enabled in REG 0x82
    //Connect DE signal to FID pin 47 when DE operation is enabled.
    //Connect  FID pin 47 to logic low when DE opeation is disabled.
    //////////////////////////////////////////

    REG 0x03 = 0xC1 // chip_ctl           
    REG 0x19 = 0x03 // csc_offset3  CSC bypassed

    REG 0x1D = 0x00 // dtg_y_sync1        
    REG 0x1E = 0x00 // dtg_y_sync2        
    REG 0x1F = 0x00 // dtg_y_sync3        
    REG 0x20 = 0x00 // dtg_cbcr_sync1     
    REG 0x21 = 0x00 // dtg_cbcr_sync2     
    REG 0x22 = 0x00 // dtg_cbcr_sync3     
    REG 0x23 = 0x00 // dtg_y_sync_upper   
    REG 0x24 = 0x00 // dtg_cbcr_sync_upper
           
    REG 0x1C = 0x70 // dman_cntl   30bit 4:4:4 input       
    REG 0x34 = 0x04 // dtg_total_pixel_msb 1056 pixels per line
    REG 0x35 = 0x20 // dtg_total_pixel_lsb
    REG 0x36 = 0x80 // dtg_linecnt_msb    
    REG 0x37 = 0x01 // dtg_linecnt_lsb    
    REG 0x38 = 0x87 // dtg_mode      VESA slave     
    REG 0x39 = 0x22 // dtg_frame_field_msb 628 line per frame/field
    REG 0x3A = 0x74 // dtg_frame_size_lsb 
    REG 0x3B = 0x74 // dtg_field_size_lsb 
    REG 0x4A = 0x8C // csm_mult_gy_msb    
    REG 0x4B = 0x44 // csm_mult_bcb_rcr_msb
    REG 0x4C = 0x00 // csm_mult_gy_lsb    
    REG 0x4D = 0x00 // csm_mult_bcb_lsb   
    REG 0x4E = 0x00 // csm_mult_rcr_lsb   
    REG 0x4F = 0xC0 // csm_mode           
    REG 0x70 = 0x80 // dtg_hlength_lsb   HSOUT = 128 pixels 
    REG 0x71 = 0x00 // dtg_hdly_msb       
    REG 0x72 = 0x01 // dtg_hdly_lsb       
    REG 0x73 = 0x05 // dtg_vlength_lsb  VSOUT=4 lines ( use 1 more than desired width)  
    REG 0x74 = 0x00 // dtg_vdly_msb       
    REG 0x75 = 0x01 // dtg_vdly_lsb       
    REG 0x76 = 0x00 // dtg_vlength2_lsb   
    REG 0x77 = 0x07 // dtg_vdly2_msb      
    REG 0x78 = 0xFF // dtg_vdly2_lsb      
    REG 0x79 = 0x00 // dtg_hs_in_dly_msb  
    REG 0x7A = 0x00 // dtg_hs_in_dly_lsb , use to adjust horizontal alignment
    REG 0x7B = 0x00 // dtg_vs_in_dly_msb  
    REG 0x7C = 0x00 // dtg_vs_in_dly_lsb  
    REG 0x82 = 0xDB // pol_cntl  HSout/VSout polarities ++, DE enabled in VESA mode, set to 0x5B  to disable DE operation      

    END_DATASET

    //////////////////////////////////////////////////////////////////////////////////////////////////////
    //"THS8200_1024x768x60Hz - 65MHz DE Blanking Enabled HS/VS-/-"
    //////////////////////////////////////////

    REG 0x03 = 0xC1 // chip_ctl           
    REG 0x19 = 0x03 // csc_offset3  CSC bypassed

    REG 0x1D = 0x00 // dtg_y_sync1        
    REG 0x1E = 0x00 // dtg_y_sync2        
    REG 0x1F = 0x00 // dtg_y_sync3        
    REG 0x20 = 0x00 // dtg_cbcr_sync1     
    REG 0x21 = 0x00 // dtg_cbcr_sync2     
    REG 0x22 = 0x00 // dtg_cbcr_sync3     
    REG 0x23 = 0x00 // dtg_y_sync_upper   
    REG 0x24 = 0x00 // dtg_cbcr_sync_upper
           
    REG 0x1C = 0x70 // dman_cntl   30bit 4:4:4 input       
    REG 0x34 = 0x05 // dtg_total_pixel_msb 1344 pixels per line
    REG 0x35 = 0x40 // dtg_total_pixel_lsb
    REG 0x36 = 0x80 // dtg_linecnt_msb    
    REG 0x37 = 0x01 // dtg_linecnt_lsb    
    REG 0x38 = 0x87 // dtg_mode      VESA slave     
    REG 0x39 = 0x33 // dtg_frame_field_msb 806 line per frame/field
    REG 0x3A = 0x26 // dtg_frame_size_lsb 
    REG 0x3B = 0x26 // dtg_field_size_lsb 
    REG 0x4A = 0x8C // csm_mult_gy_msb    
    REG 0x4B = 0x44 // csm_mult_bcb_rcr_msb
    REG 0x4C = 0x00 // csm_mult_gy_lsb    
    REG 0x4D = 0x00 // csm_mult_bcb_lsb   
    REG 0x4E = 0x00 // csm_mult_rcr_lsb   
    REG 0x4F = 0xC0 // csm_mode           
    REG 0x70 = 0x88 // dtg_hlength_lsb   HSOUT = 136 pixels 
    REG 0x71 = 0x00 // dtg_hdly_msb       
    REG 0x72 = 0x01 // dtg_hdly_lsb       
    REG 0x73 = 0x07 // dtg_vlength_lsb  VSOUT=6 lines ( use 1 more than desired width)  
    REG 0x74 = 0x00 // dtg_vdly_msb       
    REG 0x75 = 0x01 // dtg_vdly_lsb       
    REG 0x76 = 0x00 // dtg_vlength2_lsb   
    REG 0x77 = 0x07 // dtg_vdly2_msb      
    REG 0x78 = 0xFF // dtg_vdly2_lsb      
    REG 0x79 = 0x00 // dtg_hs_in_dly_msb  
    REG 0x7A = 0x00 // dtg_hs_in_dly_lsb , use to adjust horizontal alignment
    REG 0x7B = 0x00 // dtg_vs_in_dly_msb  
    REG 0x7C = 0x00 // dtg_vs_in_dly_lsb  
    REG 0x82 = 0xC3 // pol_cntl  HSout/VSout polarities --, DE enabled in VESA mode, set to 0x43  to disable DE operation      

    END_DATASET

    ///////////////////////////////////////////////////////////////////////////////////////////////////////////////

    //"THS8200_1024x768x75Hz - 78.75MHz DE Blanking Enabled HS/VS+/+"

    //////////////////////////////////////////

    REG 0x03 = 0xC1 // chip_ctl           
    REG 0x19 = 0x03 // csc_offset3  CSC bypassed

    REG 0x1D = 0x00 // dtg_y_sync1        
    REG 0x1E = 0x00 // dtg_y_sync2        
    REG 0x1F = 0x00 // dtg_y_sync3        
    REG 0x20 = 0x00 // dtg_cbcr_sync1     
    REG 0x21 = 0x00 // dtg_cbcr_sync2     
    REG 0x22 = 0x00 // dtg_cbcr_sync3     
    REG 0x23 = 0x00 // dtg_y_sync_upper   
    REG 0x24 = 0x00 // dtg_cbcr_sync_upper
           
    REG 0x1C = 0x70 // dman_cntl   30bit 4:4:4 input       
    REG 0x34 = 0x05 // dtg_total_pixel_msb 1312 pixels per line
    REG 0x35 = 0x20 // dtg_total_pixel_lsb
    REG 0x36 = 0x80 // dtg_linecnt_msb    
    REG 0x37 = 0x01 // dtg_linecnt_lsb    
    REG 0x38 = 0x87 // dtg_mode      VESA slave     
    REG 0x39 = 0x33 // dtg_frame_field_msb 800 line per frame/field
    REG 0x3A = 0x20 // dtg_frame_size_lsb 
    REG 0x3B = 0x20 // dtg_field_size_lsb 
    REG 0x4A = 0x8C // csm_mult_gy_msb    
    REG 0x4B = 0x44 // csm_mult_bcb_rcr_msb
    REG 0x4C = 0x00 // csm_mult_gy_lsb    
    REG 0x4D = 0x00 // csm_mult_bcb_lsb   
    REG 0x4E = 0x00 // csm_mult_rcr_lsb   
    REG 0x4F = 0xC0 // csm_mode           
    REG 0x70 = 0x60 // dtg_hlength_lsb   HSOUT = 96 pixels 
    REG 0x71 = 0x00 // dtg_hdly_msb       
    REG 0x72 = 0x01 // dtg_hdly_lsb       
    REG 0x73 = 0x04 // dtg_vlength_lsb  VSOUT=3 lines ( use 1 more than desired width)  
    REG 0x74 = 0x00 // dtg_vdly_msb       
    REG 0x75 = 0x01 // dtg_vdly_lsb       
    REG 0x76 = 0x00 // dtg_vlength2_lsb   
    REG 0x77 = 0x07 // dtg_vdly2_msb      
    REG 0x78 = 0xFF // dtg_vdly2_lsb      
    REG 0x79 = 0x00 // dtg_hs_in_dly_msb  
    REG 0x7A = 0x00 // dtg_hs_in_dly_lsb , use to adjust horizontal alignment
    REG 0x7B = 0x00 // dtg_vs_in_dly_msb  
    REG 0x7C = 0x00 // dtg_vs_in_dly_lsb  
    REG 0x82 = 0xDB // pol_cntl  HSout/VSout polarities++, DE enabled in VESA mode, set to 0x5B  to disable DE operation      

    END_DATASET

    ///////////////////////////////////////////////////////////////////////////////////////////////////////////////

    //"THS8200_1280x1024x60Hz - 108MHz DE Blanking Enabled HS/VS+/+"

    //////////////////////////////////////////

    REG 0x03 = 0xC1 // chip_ctl           
    REG 0x19 = 0x03 // csc_offset3  CSC bypassed

    REG 0x1D = 0x00 // dtg_y_sync1        
    REG 0x1E = 0x00 // dtg_y_sync2        
    REG 0x1F = 0x00 // dtg_y_sync3        
    REG 0x20 = 0x00 // dtg_cbcr_sync1     
    REG 0x21 = 0x00 // dtg_cbcr_sync2     
    REG 0x22 = 0x00 // dtg_cbcr_sync3     
    REG 0x23 = 0x00 // dtg_y_sync_upper   
    REG 0x24 = 0x00 // dtg_cbcr_sync_upper
           
    REG 0x1C = 0x70 // dman_cntl   30bit 4:4:4 input       
    REG 0x34 = 0x06 // dtg_total_pixel_msb 1688 pixels per line
    REG 0x35 = 0x98 // dtg_total_pixel_lsb
    REG 0x36 = 0x80 // dtg_linecnt_msb    
    REG 0x37 = 0x01 // dtg_linecnt_lsb    
    REG 0x38 = 0x87 // dtg_mode      VESA slave     
    REG 0x39 = 0x44 // dtg_frame_field_msb 1066 line per frame/field
    REG 0x3A = 0x2A // dtg_frame_size_lsb 
    REG 0x3B = 0x2A // dtg_field_size_lsb 
    REG 0x4A = 0x8C // csm_mult_gy_msb    
    REG 0x4B = 0x44 // csm_mult_bcb_rcr_msb
    REG 0x4C = 0x00 // csm_mult_gy_lsb    
    REG 0x4D = 0x00 // csm_mult_bcb_lsb   
    REG 0x4E = 0x00 // csm_mult_rcr_lsb   
    REG 0x4F = 0xC0 // csm_mode           
    REG 0x70 = 0x70 // dtg_hlength_lsb   HSOUT = 112 pixels 
    REG 0x71 = 0x00 // dtg_hdly_msb       
    REG 0x72 = 0x01 // dtg_hdly_lsb       
    REG 0x73 = 0x04 // dtg_vlength_lsb  VSOUT=3 lines ( use 1 more than desired width)  
    REG 0x74 = 0x00 // dtg_vdly_msb       
    REG 0x75 = 0x01 // dtg_vdly_lsb       
    REG 0x76 = 0x00 // dtg_vlength2_lsb   
    REG 0x77 = 0x07 // dtg_vdly2_msb      
    REG 0x78 = 0xFF // dtg_vdly2_lsb      
    REG 0x79 = 0x00 // dtg_hs_in_dly_msb  
    REG 0x7A = 0x00 // dtg_hs_in_dly_lsb , use to adjust horizontal alignment
    REG 0x7B = 0x00 // dtg_vs_in_dly_msb  
    REG 0x7C = 0x00 // dtg_vs_in_dly_lsb  
    REG 0x82 = 0xDB // pol_cntl  HSout/VSout polarities++, DE enabled in VESA mode, set to 0x5B  to disable DE operation      

    END_DATASET

  • Dear Larry

    I'm please find supportor and I send you customer problem issue of THS8200. 

    I'd like to receive  problem support or comment from Ti engineer or Marketing.

    Please support register setting value below list.

    >Application : AV-Receiver

    >customer part : FLI8668(Scaler) -> THS8200(V-encoder)

    >Question : 1920 x 1080p @24Hz / progressive / RGB 4:4:4, 10-BIT

    from Eddy

    eddy.lee@avnet.com

  • Hi Eddy,

    I need some clarification on this format.

    Is the scaler output RGB, requring an RGBin/RGBout setup for the THS8200?

    Is the THS8200 input format for 1080p24 3x10-bit 4:4:4 RGB only?

    Regards,

    Larry

     

  • Dear Larry

    Customer other timings setting is done and Only need this timing.

    I hope of your help.

    from Eddy

     

     

     

  • Eddie,

    The settings below are for 1080p24 RGB in/RGB out, similar to the graphics settings used before.  Discrete HS and VS sync inputs and outputs must be used.  1080p24 YPbPr with tri-level sync insertion will require a different setup.   I am not sure which type of setup is needed.

    DATASET_NAME,"THS8200_1920x1080x24Hz - 74.25MHz RGB in RGB out, DE Blanking Enabled HS/VS+/+"

    REG 0x03 = 0xC1 // chip_ctl           
    REG 0x19 = 0x03 // csc_offset3  CSC bypassed

    REG 0x1D = 0x00 // dtg_y_sync1        
    REG 0x1E = 0x00 // dtg_y_sync2        
    REG 0x1F = 0x00 // dtg_y_sync3        
    REG 0x20 = 0x00 // dtg_cbcr_sync1     
    REG 0x21 = 0x00 // dtg_cbcr_sync2     
    REG 0x22 = 0x00 // dtg_cbcr_sync3     
    REG 0x23 = 0x00 // dtg_y_sync_upper   
    REG 0x24 = 0x00 // dtg_cbcr_sync_upper
           
    REG 0x1C = 0x70 // dman_cntl   30bit 4:4:4 input       
    REG 0x34 = 0x0A // dtg_total_pixel_msb 2750 pixels per line
    REG 0x35 = 0xBE // dtg_total_pixel_lsb
    REG 0x36 = 0x80 // dtg_linecnt_msb    
    REG 0x37 = 0x01 // dtg_linecnt_lsb    
    REG 0x38 = 0x87 // dtg_mode      VESA slave     
    REG 0x39 = 0x44 // dtg_frame_field_msb 1125 line per frame/field
    REG 0x3A = 0x65 // dtg_frame_size_lsb 
    REG 0x3B = 0x65 // dtg_field_size_lsb 
    REG 0x4A = 0x8C // csm_mult_gy_msb    
    REG 0x4B = 0x44 // csm_mult_bcb_rcr_msb
    REG 0x4C = 0x00 // csm_mult_gy_lsb    
    REG 0x4D = 0x00 // csm_mult_bcb_lsb   
    REG 0x4E = 0x00 // csm_mult_rcr_lsb   
    REG 0x4F = 0xC0 // csm_mode           
    REG 0x70 = 0x2C // dtg_hlength_lsb   HSOUT = 44 pixels 
    REG 0x71 = 0x00 // dtg_hdly_msb       
    REG 0x72 = 0x01 // dtg_hdly_lsb       
    REG 0x73 = 0x06 // dtg_vlength_lsb  VSOUT=5 lines ( use 1 more than desired width)  
    REG 0x74 = 0x00 // dtg_vdly_msb       
    REG 0x75 = 0x01 // dtg_vdly_lsb       
    REG 0x76 = 0x00 // dtg_vlength2_lsb   
    REG 0x77 = 0x07 // dtg_vdly2_msb      
    REG 0x78 = 0xFF // dtg_vdly2_lsb      
    REG 0x79 = 0x00 // dtg_hs_in_dly_msb  
    REG 0x7A = 0x00 // dtg_hs_in_dly_lsb , use to adjust horizontal alignment
    REG 0x7B = 0x00 // dtg_vs_in_dly_msb  
    REG 0x7C = 0x00 // dtg_vs_in_dly_lsb  
    REG 0x82 = 0xDB // pol_cntl  HSout/VSout polarities ++, DE enabled in VESA mode, set to 0x5B  to disable DE