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DAC3484: DATA interface problem (applicable to DAC3482 too)

Lior Kissos
Prodigy 60 points
Part Number: DAC3484

Hi,

We have succesfully implemented  DAC3484 in an old card, where it was connected to a Xilinx FPGA (Kintex 7). Nowadays, we have decided to use the same device (DAC3484) fed with the same FPGA firmware on a new card where it was still connected to a Xilinx FPGA (however different; Xilinx Ultrscale).

the DAC3484 is configured to drive a real IF carried signal, while driven by a complex baseband signal:  functions as an IQ modulator and makes use of the internal PLL as well as of the interpolation chain.

When we observe the analog reconstructed signal (Spectrum analyzer), we notice an impairment symmetric to the "legal" signal with respect to the Fc (center frequency). We suspect that the baseband signal driven by the FPGA is erronousely interpreted, but wonder what it might be due to. Reminder; we use an old debugged firmware.

Might it be due to timing issues of the LVDS data bus? any idea?

Thanks,

Lior

  • 0
    TI__Guru* 91947 points

    Lior,

    It is possible. Is this a TI DAC EVM that you are using? Is the clocking setup the same way? How are the results if you slow everything down? This should improve if it is a marginal timing issue. Are you getting any DAC errors such as FIFO collision, FIFO away, DACCLK gone, ect....?

    Regards,

    Jim

  • 0 in reply to jim s
    Prodigy 60 points

    Hi Jim,

    Thanks for your reply.

    • We are using the DAC3484 on 2 different self designed boards, not the EVM. One of them (the old) has a well functioning DAC3484. They differ on their layout and the feeding FPGA
    • Clocking setup: both the external clocking chain (feeding the DACCLK input) and the internal PLL are configured exactly as on the old well functioning card
    • We have not tried to slow down. This might be a good idea fpr debugging
    • FIFO collision etc.: another good idea. we weren't aware of. will try this as well

    I will update

    Thanks a lot!

    Lior