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DAC37J82: DAC37J82 Questions

Max Han
Intellectual 2260 points
Part Number: DAC37J82
  1. Can you share FPGA firmware of EVM to united image? They want to build their own system.
  2. FUSE controlled, what’s meaning of the 1 fuse controlled? Does 1 mean enter sleep mode and 0 mean go out of sleep mode? Can it be read and written? Can this bit be written one time or many times?
  3. Table 90 in datasheet, serdes_ clk_sel, set this bit 0 to choose DACPLL or DACCLK from the pins?

 

  • 0
    TI__Guru* 91947 points

    Max,

    For config26, the words "Fuse controlled" should not be present here. This is a typo. This bit is set to '1" by default and the DAC PLL is in sleep mode.

    For config49, this is a typo as well. The default for this bit is "0".

    For Config59, with the default setting of "0", the serdes_clk_sel is set to DACCLK.

    The EVM CPLD firmware is attached.

    Regards,

    Jim

      CPLD files.zip

  • 0 in reply to jim s
    TI__Intellectual 2260 points

    Hi Jim,

    thanks.

    another question.

    1. How to set Bit15:13 to enable loss of signal detection? 111? 

    2. How to set Bit4:2 to choose 16bit or 20bit? do we need to change hardware connection when change 16bit to 20bit?

    thanks.