• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Subscribers 46 subscribers
  • Views 405 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

CLK source for ADS1271 from ethernet phy

Marko Pavlin40249
Prodigy 50 points
Other Parts Discussed in Thread: ADS1271

I have microcontroller with ethernet PHY which has 25MHz output and I would like to use that signal for ADS1271 master clock source. Is this common practice? I would like to optimize the design and reduce BOM for one oscillator. Is there any special design trick or rule to avoid additional noise in the system since PHY and ADS are quite distant on PCB.

 

Thanks !

 

Marko

  • 0
    TI__Guru* 97585 points

    Marko,


    I haven't heard of an application like this before, but that doesn't mean that it hasn't been done.

    While I'm not that familiar with the PHY clock in ethernet, the master clock in most of the ADCs in the product line is typically divided by 2 (at least) before being used in the digital section. This can have the effect of cleaning the clock, and certainly can reduce problems coming from imbalanced duty cycles.


    Joseph Wu

  • 0
    TI__Guru* 97585 points

    Marko,


    I just checked with one of the designers for the ADS1271 and while the analog section runs on fclk/2, the digital may not and might run on fclk directly. I'll try to get some confirmation on this, but the point is that you may need a cleaner clock than I'd originally expected.


    Joseph Wu

  • 0 in reply to Joseph Wu
    Prodigy 50 points

    Would it be better to use a high speed clock buffer to clean up the clock ? 25MHz clock is generated from 50MHz clock (÷2) and has 50% duty cycle.

  • 0 in reply to Marko Pavlin40249
    TI__Guru* 97585 points

    Marko,


    If you're concerned about noise across a PCB, the clock buffer may be fine. However, I think that using a 50MHz clock and dividing it down by 2 would be the best solution. I've never had to send that high speed of a clock across a board and I'm not sure how the signal would maintain it's integrity.


    Joseph Wu