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Hi,
When changing DCLOCK speed and timing, I want to check the DC characteristics and the relation of the input current of REF
I mailed it.
Please respond to this question.
1.When delaying only f_CLK with the specification condition (VDD=+5V) on the Datasheet (for example, 2.4MHz -> 24kHz)
Is there a change in DC characteristics?
If there is, can you give me reference data?
In other words
ELECTRICAL CHARACTERISTICS conditions are fSAMPLE=100kHz, fCLK=2.4MHz it is specified by.
For example, when using fSAMPLE=1kHz and fCLK=24kHz,
are there changes in ELECTRICAL CHARACTERISTICS parameters (specifications)?
2.In the data sheet, it is described as "reference input current depends on the conversion rate of the ADS8325."
When changing the frequency and timing of DCLOCK as shown in (a), (b), (c) of the waveform diagram,
Is there a change in the current flowing through the REF pin?
(When REF terminal is attached with 47 μF capacitor)
best regards
Hi, Rahul san
I appreciate your early support.
2) Please let me check again for the answer.
I understood that the reference power supply current changes with the conversion rate.
How much is the changing reference current value?
Is it 1mA (typ) and 1.5mA (max) of "Reference input current" written in Datasheet page4?
best regard
cafain
Rahul san
I will also consider REF 6025.
I appreciate the detailed support.
Regards,
Cafain
Hi, rahul san
In addition please let me question the following 3 points.
(1) When timing from CS assertion to sampling start is changed from (b) to (c)
is there a difference in the reference current ?
(2) Figure37 shows that the reference current is 80uA when VDD=5V and Sample Rate =10kHz,
but how much is this (error) as a variation of this value ?
(3) Under the condition of (2) above and with a 47μF capacitor attached to the REF terminal,
the ripple ΔV_Ref of the reference voltage during sampling is
ΔV_Ref = (I_Ref / C_Ref) × Δt
= (80 uA / 47 uF) * 50 usec (*)
≈ 80 uV
Could it be safe to think that? (Calculated with * CLK duty as 50%)
best regards
cafain
Rahul san
I appreciate the quick response.
I will comment on the question of (2).
It is the sampling rate of , VDD = 5V and Sample Rate = 10kHz (FCLK = 240 kHz).
I would like to know the reference current value of the VREF pin in this case and its current value error (variation).
I am sorry to ask you many times.
Best regards