DAC6573: Question of DAC6573 Configuration

Hi Wayne,

Please see my comments below

1. Extended Address - If we don's use extnded address - The address shuld be 1001111. ow do we connect he A2 and A3 signal?

[RP]: The I2C command format for DAC6573 is shown on page 17 figure 33. It is as follows

SLAVE ADDRESS -- CONTROL BYTE -- MSB -- LSB

The SLAVE ADDRESS as you mentioned is 1001111+R/W

The CONTROL BYTE two MSBs (page 15) corresponds to A3 and A2 pins. For example, if A3 and A2 pins are tied to logic '0' then the CONTROL BYE must be "00...."

2. WOuld you please advise how to use LDAC H/W synchronous VOUT update?

[RP]: This functionality is described on page 17 --

"Depending on the control byte, DACs are synchronously updated on the falling edge of the acknowledge signal that follows LS byte. The LDAC pin is required only when an external timing signal is used to update all the channels of the DAC asynchronously. LDAC is a positive edge triggered asynchronous input that allows four DAC output voltages to be updated simultaneously with temporary register data. The LDAC trigger should only be used after the buffer's temporary registers are properly updated through software."

3. We use 3.3V I2C. Can we connect 5V VDD, 3.3V IOVDD?

[RP]: Yes, this is described on page 25 --

"IOVDD pin powers the digital input structures of the DAC6573. For single-supply operation, IOVDD can be tied to VDD. For dual-supply operation, the IOVDD pin provides interface flexibility with various CMOS logic families—connect it to the logic supply of the system. Analog circuits and internal logic of the DAC6573 use VDD as the supply voltage. The external logic high inputs get translated to VDD by level shifters. These level shifters use the IOVDD voltage as a reference to shift the incoming logic HIGH levels to VDD. IOVDD operates from 2.7 V to 5.5 V regardless of the VDD voltage, ensuring compatibility with various logic families. Although specified down to 2.7 V, IOVDD operates as low as 1.8 V with degraded timing and temperature performance. For lowest power consumption, ensure that logic VIH levels are as close as possible to IOVDD, and logic VIL levels as close as possible to GND voltages."

Please feel free to contact us, if you need more support on this.

Thanks,

Rahul Prakash

Hi Wayne,

I would recommend that you tie LDAC pin to logic '0' if you do not intend to use it.

Best Regards,

Rahul Prakash