ADC12J2700 JESD204B setting ???

Hi,

I am using ADC12J2700 and trying to bring up our custom module. The module has only 4 transceiver lanes to work with. The parameters I am using are

fs = DEVCLK = 1000 MHz

Decimate-by-4, DDR = 1, P54 = 1, LMF = 4,2,2

I calculate the line rate and F_SYSREF as follows:

Line rate = 2.5 * Fs =  2.5Gb/s

F_LMFC = Line rate/(K*F*10) = 2.5Gb/s / (10*2*10) = 12.5 MHz

F_SYSREF = 12.5 MHz / n

Is this correct ?

And what should be the register values?

Also should the PLL be locked bit 2 of register 0x205 for the ADC to work?

Rgds,

Stephen

Hi Stephen

The register settings above have SYSREF processing turned off. Here is the reason for that:

For most ADC devices, harmonic energy from the SYSREF signal can couple into the device and create spurs in the converted spectrum. For this reason SYSREF should be turned off unless it is needed to be active to re-align the ADC to the system SYSREF. If SYSREF is DC-coupled to the ADC, then SYSREF can be stopped at logic 0 or logic 1 and SYSREF processing can remain enabled. In cases where SYSREF is AC-coupled, SYSREF processing must first be disabled before turning off SYSREF at the source.

The above register settings are OK because the ADC12J2700 will self-generate the internal LMFC without SYSREF being applied. If you only have a single ADC system and don't need deterministic latency then you never need to have the ADC SYSREF active. This can eliminate any extra overhead of enabling/disabling SYSREF.

Best regards,

Jim B

Thanks Jim for the quick response. I now have the PLL locked.

Rgds,

Stephen

Hi Jim,

i now have the PLL locked but I still dont see any activity on the Serial transceivers. What registers do I need to set in order to get the ADC Test pattern working.

Thanks and Regards,

Stephen

Stephen,

I am covering for Jim B. while he is on vacation. What test patterns are you trying to use? Just for my info, what FPGA are you interfacing to?

Regards,

Jim S.

Hi Jim,

We have a customer with a big potential (both for us and TI) and we need to resolve the issue as soon as possible other wise we will loose this customer. As mentioned above I am using 4 transceivers links and dont see any activity with the above settings.

Before testing the ADC with external Analog input I want to make sure the ADC is functional and the links are working with Internal Pattern generator. Can you please tell me what registers I need to set in the ADC and JESD Core to get this working?

Thanks and Regards,

Stephen

Stephen,

The attached document shows all the settings I used to get this to work with our TSW14J56EVM.

Regards,

Jim S.

ADC12J2700_test pattern mode.pptx

Hi Jim,

Thanks for the response, but still no luck. In the first slide it says NCO = 700MHz. Where do I set that?

Rgds,

Stephen

Stephen,

Write 0x0 to addresses 0x210, 211, and 212. Write 0xC0 to address 0x213.

Regards,

Jim 

Hi Jim,

I am debugging the signals using JTAG and I can see the signals going into the JESD core but dont see anything coming out of it. Can you tell me what should I look for in order to see the data coming out of the JESD core?

Thanks and Regards,

Stephen

Hi Jim,

Is it possible to get the ADC12J2700 EVM on loan?

www.ti.com/.../adc12j2700evm

We want to make sure if our core is correct and the fastest way is too use the EVM.

Best Rgds,

Stephen

Hi Stephen

I'm looking into your EVM request.

I should have some information by Monday.

Best regards,

Jim B

Thanks Jim,

Really appreciate it. Also I would like to know what registers I should read in the ADC to make sure the JESD link is up and running. As per my understandinbg its the JESD Status register

0x205 = 0x4

is this right?

Rgds,

Stephen

Hi Stephen

If the link is up the SYNC_STATUS bit will be 1 (SYNC~ de-asserted) and the LINK_UP bit will be 1.

So Register 0x205h will be 011x xy00.

It is not necessary for either Aligned or Realigned to be set for the link to be up. With no SYSREF applied the ADC can self-generate the internal LMFC without it being Aligned to SYSREF.

For modes with P54=1, then 'y' (PLL_LOCKED) must also be 1 for the link to be up.

Best regards,

Jim B

Thanks Jim. When I read 0x205 register the value is 0x4 when it should be 0x64. Where do think the problem is setting upu the ADC or the FPGA core?

Rgds,

Stephen

1323.ADC_Circuit.pdfHi Jim,

I am also including our ADC circuit to see if there is any error in the design. Can you have a quick look at it to see if the circuit is correct?

Rgds,

Stephen

Hi Jim,

We are still struggling to get the ADC work. Havent got the EVAL board yet. I am trying to use the ADC in 8-lane mode as provided in the demo by TI.

fs = DEVCLK = 1000 MHz

Decimate-by-1, DDR = 1, P54 = 0, LMF = 8,8,8

Line rate = 2.0 * Fs =  2.0Gb/s

F_LMFC = Line rate/(K*F*10) = 2.0Gb/s / (32*8*10) = 0.781 MHz

F_SYSREF = 0.781 MHz / n

Ref_clk = 200 MHz

Core_clk (Global Clk) = 50 MHz

Can you please help me with the values for the parameters in JESD204-PHY block and JESD204B core?

Rgds,

Stephen

Hi Stephen

According to the information I have, the Xilinx REFCLK and Core clock should both be at Lane rate / 10 when the lane rate is at 2 Gbps. So both should be set to 200 MHz.

See section 6 of the TSW14J10EVM Users Guide which can be downloaded here: http://www.ti.com/tool/tsw14j10evm#Technical%20Documents

The SYSREF frequency will be 0.78125 MHz for that mode and K=32.

The JESD204B core values used with the VC707 and ADC12J4000EVM in DDC Bypass Mode, with K=4 are shown below. The critical parameters for this example IP are F and K. The M value of 4 is misleading and isn't used directly in the firmware as we store all of the octet data into RAM and then post-process using software to extract the 12 bit ADC samples.

JESD IP Core_CS=0
JESD IP Core_F=8
JESD IP Core_HD=1
JESD IP Core_K=4
JESD IP Core_L=8
JESD IP Core_Lane_Enable=255
JESD IP Core_M=4
JESD IP Core_N=12
JESD IP Core_NTotal=12
JESD IP Core_S=1
JESD IP Core_SCR=1
JESD IP Core_Tailbits=4
JESD IP Core_LaneSync=1
JESD IP Core_Subclass=1

Best regards,

Jim B

Hi Stephen

Yes, for the Rev A EVM, the LMK04828 input clock is always ADC_CLK/2. So for some conditions with low input clock frequency the clock divider value becomes smaller than is possible to set with even integer divides.

I'm looking into other possible solutions for your case including tracking down one of the earlier revision EVMs that allows 1:1 clocking of the LMK04828 at low ADC clock rates.

One simple fix for the short term would be to try using ADC Fclk = 2 GHz and see if you can get everything working in those conditions. Since lane rate will be 4 Gbit/sec the divide values are all workable.

Best regards,

Jim B

Hi Jim,

Thanks for the reply. I am now getting data from the JESD core after using 2.7 GHz sampling clock with the following settings

0x202 = 0x49 (Modified RPAT Test  Mode)

Hi Jim,

We have to get our ADC card working by the end of this month and we are not getting anywhere even with the EVAL board. I read the ADC reference manual and it seems that the ADC test pattern will only work when all the 8-lanes are used, but I was provided a power point which shows using the ADC test pattern using 4 lanes. 

I think the easiest way is to use "High Speed Data Converter Pro" software, for which I need the TSW14J10EVM module. Can you please loan us this module or what is the easiest way to get this module?

Really appreciate your help.

Rgds,

Stephen

Hi Stephen

From your earlier post it looks like you are getting some data through the link in D20 DDR mode, but it's not clear it is the correct data. I set up an EVM in D1 DDR and D20 DDR modes at 2700 MHz clock and gathered some data that may help for comparison purposes.

The data exported from HSDC Pro Time Domain view is in this file:

/cfs-file/__key/communityserver-discussions-components-files/73/2330.ADC12Jxx00-D20-DDR-Output-Data.xlsx

The HSDC Pro plot data is in this .ppt.

/cfs-file/__key/communityserver-discussions-components-files/73/8446.ADC12J2700-debug.pptx

Please note that in D20 mode, the output data is signed 2's complement format. We normally pre-process the data before display in HSDC Pro by XORing the sign bit with 1 to change it to unsigned data. Some of the spreadsheet and plots were processed with this feature disabled to help illustrate the raw data coming out of the link, while others were change to the normal processing to make the waveforms give the expected shape. The only difference is the polarity of the MSbit.

I don't have a spare TSW14J10EVM, but they are readily available at the TI store here: https://store.ti.com/TSW14J10EVM-JESD-Converter-EVM-to-FPGA-EVM-adapter-P5235.aspx

I hope this is helpful.

Best regards,

Jim B

Thanks Jim,

Really appreciate it. I will order one TSW14J10EVM  right away. In the mean time can you please send me the register dump of the EVM for all different modes listed in the PPT above so that I can load the values from the text file It seems that my settings are not right.

Rgds,

Stephen

Hi Jim,

Is it possible to have a conference call for 30 mins on skype or webex so that I can share my screen and you walk me through. I am setting up the EVM exactly as you suggest but no result. We only have two more weeks to deliver.

My Skype ID is "Stephensdsp"

Thanks and Regards,

Stephen

Hi Stephen

I'm traveling this week but I'll see what I can set up.

I'll send you private message with details.

Best regards,

Jim B

Hi Jim,

The inversion of the lanes in the FPGA did not work. With the inversion JESD core does not output any data.

Can you please provide the core that does the inversion for the example design?

We have ordered the adapter board maybe for Xilinx boards the adapter board reswaps the lanes. Will have to wait and see how that works.

Rgds,
Stephen

Hi Jim,

I hope you had a good trip to china. We managed to get the EVM working with the our FPGA board but when I replace the EVM with our FMC card it does not generate the SYNC signal from the JESD Core. I have made sure all the register settings are right.

Can you tell me what can go wrong for the JESD to not generate the SYNC signal?

Also is it possible for me to make a visit to your facility next week as we are in a crunch situation.

Rgds,

Stephen

Hi Stephen

Can you confirm that the combination that worked was:

• ADC12J2700EVM plus PXIe700 FMC Carrier board (please let me know if the TSW14J10EVM was needed to make this combination work).

and the combination that isn't working is:

• FMC-DAQ2p5 plus PXIe700 FMC Carrier board

Can you provide the schematics for the FMC-DAQ2p5 board and register settings used with the ADC in that platform? If needed we can do this via PM or email off-line.

I believe as long as the FPGA is receiving the expected JESD204B clocks and SYSREF it should assert SYNC even before receiving any JESD204B data from the ADC. I will confirm this on Monday.

I'll send a PM to discuss availability next week.

Best regards,

Jim B

Hi Jim,

Yes, the working combination is  ADC12J2700EVM plus PXIe700 FMC Carrier board (without the TSW14J10EVM)

FMC-DAQ2p5 plus PXIe700 FMC Carrier board doesn't work.

Included the schematic for FMC-DAQ2p5. Register settings are as follows:

---------------------------------------------------------------------------------------------------------------------------------

(REG_CONF_A_0x0,         0xBC);            // RESET
(REG_CONF_A_0x0,         0x3C);            // DEASSERT RESET
(REG_POR_0x21,         0x00);                 // Initiate reset of all registers
(REG_POR_0x21,         0x01);                 // De-assert reset
(REG_CLKGEN0_0x30,     0x00);            // SYSREF receiver and processor off
(REG_SERCFG_0x40,         0x04);                // Set serializer pre-emphasis for high speed PCB
(REG_T_CAL_0x66,         0x03);                // Foreground calibration mode with timing optimization enabled
(REG_OVR_N_0x208,         0x07);                // Change over-range processing to longest interval
(REG_CAL_CFG1_0x51,     0x84);                // Calibration optimized for large signals
(REG_JESD_CTRL1_0x201, 0xDE);                // A6 Scrambler on, KM1 = 23, DDR, JESD disabled
(REG_ADC_PAT_OVR_EN_0x58,    0x00);                // EN ADC Test pattern        
(REG_DDC_CTRL1_0x200,     0x32);                // 6.02dB gain, decimate-by-4
(REG_JESD_CTRL2_0x202, 0x84);                // P54 PLL on, Differential SYNC, Normal data mode
(REG_JESD_CTRL1_0x201, 0xDF);                // A7 Scrambler on, KM1 = 23, DDR, JESD enabled
(REG_CAL_CFG0_0x50,     0x0E);                // Initiate a foreground calibration       
(REG_NCO_PSET0_0x210, 0x12);                    
(REG_NCO_PSET0_0x211, 0x11);                    
(REG_NCO_PSET0_0x212, 0x11);                    
(REG_NCO_PSET0_0x213, 0x11);

---------------------------------------------------------------------------------------------------------------------------------

The clocks provided are as follows

ADC_DEVCLK = 1600 MHz

ADC_SYSREF = 8.33 MHz

FPGA_REFCLK = 200 MHz

FPGA_CORECLK = 100 MHz

FPGA_SYSREF = 8.33 MHz

Thanks and Regards,

Stephen2577.ADC_Circuit.pdf

Hi Stephen

Your schematic looks OK as far as I can see. Is the ADC DEVCLK AC coupled from the clock driver as required?

The only question I have about the register settings is the value of REG_JESD_CTRL2 which is 0x84h. This disables the differential SYNC and uses the single ended SYNC. I believe that is your desired configuration but wanted to confirm.

I would also recommend setting the NCO frequency/phase values before enabling the JESD204B interface. This isn't super important if you are only using a single ADC, but if you needed to synchronize the NCO of multiple ADC devices then it would be needed.

All of the clock frequencies you list are correct for a Xilinx FPGA.

I confirmed on my setup with Altera FPGA that the firmware does assert SYNC even if the ADC board is not outputting clocks or data.

Best regards,

Jim B

Hi Jim,

Yes, as you can see our FMC has providion for both differentila and single ended SYNC signal.So I was trying both this one was using SE Sync. We are using only one ADC but I will implement your recommendation and see if that gives anything.

On Xilinx FPGA the SYNC signal is only asserted when the clocks are present.

Rgds,

Stephen

Hi Jim,

Didnt make any difference. Its behaving the same.

What else can I look at to debug?

Rgds,

Stephen

Hi Stephen

I would compare all of the detailed signals at the FMC connector. Something must be different between the ADC EVM and your DAQ module in terms of location, signal level, etc.

I don't have that information from your board, so I don't know exactly how the clocking circuitry and other FMC signal routing are done.

Regards,

Jim B