Using ADC12J4000EVM GUI to load register configuration

Jim,

Thanks. This is very helpful. Would you mind enlighten me which LMK*.cfg will be loaded based on when the "Program clock and ADC" button is clicked when my configuration is shown below? The reason I ask is that I did not see a "*_Fs_4000Msps" (since the clock I select is 4000Msps), but only saw config files associated with Fs_3500Msps or Fs_1550Msps

Thanks, Bing

Jim, thanks a lot!

Jim,

I have a couple more questions that maybe you can help to clarify -- I am the Bypass, Onboard clocking and 4000 MHz clock setting, what would be the devclk value and the corresponding FPGA clk? If it 4000MHz (>3125MHz), then the divider setting should be 40? But the LMK04828 registers 0x100 and 0x110 (for clk0 and clk4) both had divider = 10. Is there a test point that I can use to check the clock on the scope?

My second question is about the LMN values, I tried to go by table 11 in the ADC12J4000 datasheet,  but I can't seem to find the corresponding values in ADC12J4000_BYPASS.ini file in TSW14J56 revD ADC file directory? 

Finally, can you help to explain about the following bit packing configuration in the same file too? I can't seem to find the corresponding information in ADC12J4000 datasheet (tables 12 and 13) either..

\\1 -  Data are bit packed(MSB aligned) without any padded zeroes

Bit Packing Channel Pattern =C1S1[11:0],C1S9[11:0],C1S17[11:4],C1S2[11:0],C1S10[11:0],C1S18[11:4],C1S3[11:0],C1S11[11:0],C1S19[11:4],C1S4[11:0],C1S12[11:0],C1S20[11:4],C1S5[11:0],C1S13[11:0],C1S21[11:4],C1S6[11:0],C1S14[11:0],C1S22[11:4],C1S7[11:0],C1S15[11:0],C1S23[11:4],C1S8[11:0],C1S16[11:0],C1S24[11:4],C1S17[3:0],C1S25[11:0],C1S33[11:0],T[4],C1S18[3:0],C1S26[11:0],C1S34[11:0],T[4],C1S19[3:0],C1S27[11:0],C1S35[11:0],T[4],C1S20[3:0],C1S28[11:0],C1S36[11:0],T[4],C1S21[3:0],C1S29[11:0],C1S37[11:0],T[4],C1S22[3:0],C1S30[11:0],C1S38[11:0],T[4],C1S23[3:0],C1S31[11:0],C1S39[11:0],T[4],C1S24[3:0],C1S32[11:0],C1S40[11:0],T[4]

Thanks again, Bing

Hi Bing

For that case with the Rev A EVM the clocks are as follows:

For Fs = 4000 MSPS, F_devclk = 4000 MHz.

There is a divide by 2 circuit between the TRF3765 output and the LMK04828 clock input, so it receives F_lmk = 2000 MHz.

For DDC bypass mode, F_linerate = 2x F_devclk = 8000 Mbit/sec

The FPGA clock frequency should be F_linerate / 40 = 8000 / 40 = 200 MHz.

F_fpga = 200 MHz = F_lmk/N = 2000 MHz / N. Therefore the divider N must be equal to 10.

Regarding the LMN values. The L value is necessary, but since we're using the Bit Packing Channel Patterm method of decoding the data, the M and N values in the .ini file are not critical.

Along with L, the other critical parameters are K and F. K*F of the ADC must match the K*F used by the FPGA.

To maximize flexibility to support many different ADCs, the TSW14J56 FPGA design streams the received data octets directly into on-board RAM with no processing. The Bit Packing Channel Pattern parameters are used to decode that octet data back into 12-bit samples, discarding the 4 tail bits at the end of each frame. The exact Pattern coefficient sequence is related to the structure of the ADC data frame along and how the data from each RX lane is streamed into memory.

If you are basing your design on the TSW14J56 firmware data storage method then the Pattern parameters could be useful. If this is the case please let me know, I can provide more detail on how data is streamed to memory and how the bit Packing Channel Pattern is used to decode the data for use in HSDC Pro.

If you are writing your own code to process or store the data then it is probably better to decode the 12b samples as they are received.

Best regards,

Jim B

Jim,

Thanks a lot. I just deduced the 200MHz FPGA clock based on a formula you provided to a different user in the forum: 

Lane Rate = (ADC_Sample_Rate * N' * (10/8) * (16/15)) / Lane

But is really happy to have your confirmation.

I would greatly appreciate it if you can provide more detail on how data is streamed to memory and how the bit packing channel pattern is used to decode the data...

Thanks again, Bing

Jim,

As mentioned earlier, I will be using 4GHz clock, bypass mode no-decimation. Can you confirm the following JESD configuration is valid (this was copied from the dynamic configuration window of the HSDC Pro GUI)
* sub class 1
* L = 8
M = 4
N = 16
K = 32
F = 1

Is this compatible withe Table 12 of the ADC12J4000 datasheet? I ask since while the table is for bypass mode, no-decimation, it has LMF=8,8,8. This confuse me again...

If the configuration is correct, can I parse the data stream from according to table 12 (instead of bother you with the detail on how data is streamed to memory and how the bit packing channel pattern is used to decode the data)?

Thanks again, Bing

Hi Bing

For a design that is receiving and directly processing or decoding bypass mode no-decimation data, you should use the following configuration parameters:

L=8

M=8

F=8

K=4

N=12

N'=12

S=5

Table 12 and Table 13 are two different ways of viewing the same data transmitted by the ADC. Table 12 shows how the bypass mode is defined to comply with the JESD204B standard, with 8 interleaved converters (C0 to C7) with 5 samples per converter per frame. Table 13 shows how the samples are arranged when considered as a single input ADC with 40 samples per frame.

See this earlier post https://e2e.ti.com/support/data_converters/high_speed_data_converters/f/68/p/432366/1546687#1546687

for more information on why LMF = 888 is used even though this device is functionally a single input ADC.

I hope this is helpful.

Best regards,

Jim B

Jim,

Thanks,

I am still hope to get clarification about the JESD parameters... The parameters I listed was what I took from the dynamic configuration window of the HSDC_pro GUI when I used ADC12J4000EVM in 4GHz, bypass, no-decimation mode with TSW14J56 RevD EVM (showing below). However, we need to re-program the Altera FPGA in TSW14J56 so that we can do batch data collection. Therefore, we should use the parameters you provided? Why is it so much different from the dynamic configuration parameters values?

Thanks again.

Hi Bing

The standard firmware and High Speed Data Converter Pro software can already do batch storage and export of data in DDC Bypass Mode. You may be able to do what you need with no changes to the FPGA firmware.

There are automation features that allow this to be done from LabVIEW or other software platforms. Please take a look at the information in the High Speed Data Converter Pro directory here:

C:\Program Files (x86)\Texas Instruments\High Speed Data Converter Pro\Automation Function APIs

and here:

C:\Program Files (x86)\Texas Instruments\High Speed Data Converter Pro\HSDCPro Automation DLL

C:\Program Files (x86)\Texas Instruments\High Speed Data Converter Pro\HSDCPro Automation DLL\Manual and Examples

If you use the standard firmware and software you won't need to change any of the JESD204B parameters. The key parameters used by the HSDC Pro software and firmware are L and K*F. The resulting product K*F set in the .ini file must match K*F used in the ADC settings. In this case K*F = 32. In the ADC settings K=4 and F = 32, while in HSDC Pro K=32 and F=1 but the product is the same in both cases.

Best regards,

Jim B

Jim,

Unfortunately we can't use the standard firmware. We will need to change the FPGA code in order to capture data for each incoming trigger at a fixed frequency, buffer data, then send a batch of data to PC (Matlab variable).

So I assume we will need to change the JESD parameters for the Altera FPGA on to the values you recommended?

L=8

M=8

F=8

K=4

N=12

N'=12

S=5

Thanks again.

Jim, sorry to bug you on the same question... But can I interpret  your explanation as if I use ADC12J4000_DB1_DDR.cfg to configure ADC12J4000EVM, then the corresponding JESD parameters for the FGPA should be:

L=8 M=8 F=8 K=4 N=12 N'=12 S=5

Thanks again, Bing

Hi Bing

If you are using your own implementation of FPGA firmware those are the appropriate JESD204B parameters to use.

If your design is based on the existing configurable TSW14J56EVM capture firmware I would pass it the parameters included in the file ADC12J4000_BYPASS.ini.

Best regards,

Jim B