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ADC12J2700 Sampling question?

mingming zhu
Prodigy 200 points
Other Parts Discussed in Thread: LMK04828, ADC12J2700

Hi，

On the ADC side, the configurations are as follows.

I use LMK04828 provide  F_DEVCLK = 1250 MHz.  SYSREF=2.5/(K*F*10)=2.5/320=7.8125Mhz。

ADC12J2700
0x0021 0x00 // Initiate reset of all registers
0x0021 0x01 // De-assert reset
0x0030 0x00 // SYSREF receiver and processor off
0x0040 0x04 // Set serializer pre-emphasis for high speed PCB
0x0066 0x03 // Foreground calibration mode with timing optimization enabled
0x002B 0x13 // Change reserved register to proper setting
0x0208 0x07 // Change over-range processing to longest interval
0x0051 0x84 // Calibration optimized for large signals
0x0201 0x0E // Scrambler off, KM1 = 3, DDR, JESD disabled
0x0200 0x30 // bypass mode
0x0202 0x40 // P54 PLL off, Differential SYNC, Normal data mode
0x0201 0x0F // Scrambler off, KM1 = 3, DDR, JESD enabled  
0x0050 0x0E // Initiate a foreground calibration

Xilinx JESD204B core

addr                           data

12'h008                           32'h00000001  //

12'h00c                           32'h00000000  //Scrambling off

12'h010                           32'h00000001

12'h018                            32'h00000000

12'h020                             32'h00000007 //Octets per Frame F=8

12'h024                            32'h00000003 //Frames per Multiframe K=4

12'h028                            32'h00000007 //Lanes in use  L=8

12'h02c                              32'h00000001

12'h030                             32'h00000000

12'h034                             32'h00000000

12'h004                             32'h00000001

so I test the ADC12J2700 with Short and long transport layer test mode  is right,but  when I  test with Normal operation,FFT  results has problem？？

for example, The test input frequency is 33.25Mhz。Reference ADC12J2700 datasheet  Table 12，Therefore the sample order in time is: C0S0, C1S0, C2S0, C3S0, C4S0, C5S0, C6S0, C7S0, C1S1, C2S1, .... C7S4 for all 40 samples in one frame。Each channel data 31.25Mbps sampling rate。（31.25*40=1250）。

My question is FFT  results has problem？

  • 0
    TI__Mastermind 44680 points

    Hi mingming

    I think you have the ADC settings correct, and are decoding the data correctly. I believe there are two key causes for the issues in the FFT.

    1) Your input frequency is not coherently related to the sample rate and number of samples being used in the FFT, and you are not using FFT windowing. This can be resolved by either using some form of FFT windowing (High Speed Data Converter Pro tool uses Blackman by default), or by ensuring the input frequency is coherent. Coherency requires the ADC clock to be frequency locked to the signal generator, and the generator frequency set to a coherent frequency. If you are using the LMK04828 PLL to generate the 1250 MHz sample clock frequency based on the 100 MHz XO, it is not possible to make the sample clock and input signal coherent. In that case you will need to implement a windowed FFT.

    2) The constant SYSREF applied to the ADC is coupling into the converted signal. This is causing the spurs offset from the fundamental tone. To resolve this you can configure the LMK04828 ADC SYSREF output to only send SYSREF when requested using the SYNC input. If your ADC SYSREF input is DC-coupled this is all you need to do. If the ADC SYSREF input is AC-coupled you will need to disable ADC SYSREF processing (Register 0x030h, Bit 6) before SYSREF is discontinued.  Once the ADC SYSREF is turned off the sideband tones should disappear. The ADC SYSREF should only be enabled when needed to re-synchronize the JESD204B link.

    If you don't need to synchronize the ADC12J2700 to other devices and deterministic latency is not required, you can leave ADC SYSREF processing permanently disabled, and the ADC SYSREF signal disabled at all times. The ADC12Jxx00 devices automatically generate an internal LMFC without the application of SYSREF.

    I hope this is helpful.

    Best regards,

    Jim B