Getting started: ADC-DSP/FPGA minimum system

Francisco Eduardo Balart Sanchez

Other Parts Discussed in Thread: ADS5463, DAC5674, CDCE72010

Good day:

My name is Francisco Eduardo Balart Sánchez and i’m working in a “concept proof” project which involves digital signal processing. The project is in the phase of implementation, therefore I have to research what devices I need for such implementation and how much the “minimum system” would cost. What solution can you propose?

Here is a more detailed description of the project.

I’m trying to implement digital signal processing to an analog RF signal (CATV) with frequency ranges from 5 MHz to 200 MHz, therefore I know I have to implement a ADC then a DSP or FPGA and after a DAC (plus the signal conditioning PLL’s, etc.), but there some things I don’t understand well.

For example since my greatest frequency is 200 MHz (in which I have to recover the carrier) I try to use an ADC with at least more than the double of 200 MHz. I’ve seen some ADC’s which uses undersampling and others not, if the signal content is in al the 5-200 MHz spectrum I have to use a ADC with more or equal than 400 MSPS? Or is there a way to achieve this with undersampling?

After I choose then an ADC then I don’t know the relation of the clock needed to achieve such SPS. What is the relation between the samples per second and the ADC’s clock?

Finally the DSP or FPGA selection must meet the speed of the ADC (in the I/O bandwidth specification)

I hope the previous explain a little bit more the scope of the needs in order to help you to propose a solution (minimum system including clock, PLL, VCO, DAC, etc.).

Thanks in advance and best regards

M.S. Francisco Eduardo Balart Sánchez
dkbf73@motorola.com
Ph. +52 (81) 1301-0215

over 15 years ago

0 RJ Hopper over 15 years ago

TI__Mastermind 18095 points

For signals that occupy 5 to 200 MHz it would be best to operate the ADC at 400 MSPS or greater. TI offers a variety of 12-bit and 14-bit ADCs that operate 400 MSPS up to 1000 MSPS that would be suitable for that application. You will clock the device at the desired sampling rate (i.e. at the SPS). You can access the TI web to search for devices that fit your specific sampling speed and bit resolution requirements.

--Russell

0 Francisco Eduardo Balart Sanchez over 15 years ago in reply to RJ Hopper

Prodigy 30 points

Good day Russell:

Thanks for the quick response, i already started to see the IC's that TI offers. Regarding the project i need to build a minimum system (PLL, VCO, ADC, DSP/FPGA, DAC), i hope that with the following specifications you can help me to find the right solution for my application:

A general description of the signal processing would be:
- The RF signal pass through signal conditioning (if needed) before the ADC samples such signal, after, the ADC send the digital values of the sampled signal to the DSP/FPGA which will encrypt, digitally process, etc de data, after this, the DSP/FPGA will send the data to a serializer (or mux) and the data will travel serially to a laser driver which will send the data to a laser. After this the signal will be received by a photodiode, de-serialized (de-mux) and send to the DSP/FPGA which will de-encrypt, and digitally process the data, sending it to an DAC and finally recovering the RF signal.

Modulation used: QPSK or QAM

Frequency range: from 5 MHz to 200 MHz

Dynamic range specifications

19dBmV Nominal input @75 Ohms 8.86197726829727 mV(rms)

60 dBmV Max input @75 Ohms 994.330203663404 mV(rms)

Thanks in advance and best regards

M.S. Francisco Eduardo Balart Sánchez

dkbf73@motorola.com

Ph. +52 (81) 1301-0215

0 RJ Hopper over 15 years ago in reply to Francisco Eduardo Balart Sanchez

TI__Mastermind 18095 points

I would recommend the following for the data converters and the clocking solution:

ADS5463 12-bit 500 MSPS

DAC5674 14-bit 400 MSPS

CDCE72010 Low Jitter Clock Distribution Chip

Data converters

Data converters forum

Getting started: ADC-DSP/FPGA minimum system