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ADS131A04: simultaneously sampling of multiple ADS131A04 ADC's

Roy Geverink
Prodigy 140 points
Part Number: ADS131A04


For a new design we are looking to see if the ADC ADS131A04 is right for our designs.
We want to sample 32 or 64 channels in this design. The channels must be sampling simultaneously.
Now I see in the datasheet that the four channels into a single ADC sampling simultaneously, perfect. But how do I get this done with multiple ADCs in a chain.
I see insist that through the DRDY line the digital filter can be synchronize, but sampled the various ADCs synchronously or simultaneously? so are there start sampling on the same clock puls or is only the digital filter reseted?

  • 0
    TI__Mastermind 38745 points
    Hey Roy,

    If the devices are using the same clock and share a DRDY then they will sample simultaneously (within propagation delay for clocks, DRDY signal, etc.). Section 10.1.3 in the datasheet discusses all the various ways to daisy-chain multiple devices.

    Regards,
    Brian Pisani
  • 0 in reply to Brian Pisani
    Prodigy 140 points

    Hi Brian,

    Thank you for your reply. Sounds like we can use this device for our project.

    Since this ADC is the heart of our system we would like to be 100% sure that we understand it correctly.

    Please see the attached photo for illustrations.

    We use the setup as described in figure 103 (section 10.1.3.3.) with an input SCLK of 2 MHz. This is divided down to 1MHz in each ADC (ADC1 and ADC2 are in two different packages). All ADCs seem to take their samples on the rising edge of Fmod.

    What we see that could happen is that the rising Fmod edge of ADC1 is one SCLK period different from the Fmod rising edge of ADC2. When both ADCs take a sample on their rising edge, the sampling moment is not equal (delayed by     ½ period of the 1MHz: ½ us).

    In our opinion the internal clock divider of the ADC could cause this different Fmod, when each ADC is configured in the chain and starts automatically sampling.

    What we need to know is whether sharing the DRDY as in fig 103 results in resetting all Fmod clocks such that the rising edges align. Thus that ADC1 and ADC2 take their sample at the same time with respect to the Fmod clock.

    Thank you for your help.

    Best regards,
    Roy

  • 0 in reply to Roy Geverink
    TI__Mastermind 38745 points
    Hello Roy,

    What you described is not possible. The DRDY event will synchronize the modulator clock to the same edge for all devices. The synchronization state machine takes place at the master clock level.

    Brian
  • 0 in reply to Brian Pisani
    Prodigy 120 points

    Hello Brian,

    I respond to you on behalf of my colleague Roy.

    With respect to you reply:

    1. "The DRDY event will synchronize the modulator clock to the same edge for all devices."
      Does this mean "...sharing the DRDY as in fig 103 results in resetting all Fmod clocks such that the rising edges align" and "... that ADC1 and ADC2 take their sample at the same time with respect to the Fmod clock."
    2. "What you described is not possible"
      Which part of our text does this refer to?

    Thank you for your help!

    Best regards,

    Frank & Roy

  • 0 in reply to Frank Ambrosius
    TI__Mastermind 38745 points
    Frank, Roy,

    I mean that you have nothing to worry about :-). The daisy chained devices will sample at the same exact time if the DRDY line is shared between them. When I said it was "impossible" I was referring to the diagram you drew where the fmod edges were offset by a master clock cycle.

    Brian