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DAC8750: DAC8750 - how to connect the ISET-R terminal?

Part Number: DAC8750


The datasheet says:

Resistor RSET (used to convert the DAC voltage to current) shown in Figure 53 determines the stability of the output current over temperature. If desired, an external, low-drift, precision 15-kΩ resistor can be connected to the ISET-R terminal and used instead of the internal RSET resistor.

This description is imprecise in the following sense:

  1. Connect the resistor to ISET-R at one end and the other to what - GND? I guess so, but it is not described anywhere.
  2. If I don't want to benefit from an external resistor, what do I connect to pin ISET-R?
  3. "...the ISET-R terminal and used instead of the internal RSET resistor": How do they combine when using external resistor? 

Figure 60 only vaguely has some hints - but notice that on this drawing the pin name ISET-R is absent - which is strange.

thanks for clarifications

  • notice that figure 62 could be made more helpful by including the ISET-R in the diagram - used or not. From this diagram you can guess that the pin can be left not connected. But I would rather not guess. Note for instance that DVDD-EN _is_ included and marked as not connected (indicating that this pin has internal pull-ups)
  • Henning,

    Your feedback is noted.

    In Figure 60 the internal RSET is used which is connected to the low-side of T1 / inverting input of A1 via a switch and the low-side of the internal RSET is internally connected to ground. As you noted the ISET-R pin is not illustrated in Figure 60, if it were to be included it would simply be a direct connection from the same point (low-side of T1 / inverting input of A1), exactly what is illustrated in Figure 61. With that in mind...

    henning larsen said:
    Connect the resistor to ISET-R at one end and the other to what - GND? I guess so, but it is not described anywhere.


    Correct. The connection scheme should be similar to what is shown for the internal RSET, basically what is shown in Figure 61 except perhaps excluding the optional HART input filter Cin and Rin.

    henning larsen said:
    If I don't want to benefit from an external resistor, what do I connect to pin ISET-R?


    Since there is no switch involved here to disconnect the ISET-R pin from the rest of the circuit leaving it floating is one option. Connecting it to any DC potential would however cause some unexpected performance, so it should never be direct connected to ground for example. In applications that may be exposed to radiated emissions it is advisable to AC couple this input pin to ground to reduce the content that may couple into the current output.

    henning larsen said:
    "...the ISET-R terminal and used instead of the internal RSET resistor": How do they combine when using external resistor?


    I'm not sure if I have understood the question correctly on this one, but I think it just relates to some poor phrasing in the text that suggests there is some possible method of using both internal and external RSET resistors. While it may be possible to do such a thing, it would impact device performance at the least in the respect that the outputs would no longer be as described in the datasheet as you would effectively have two resistors in parallel used to form the current setting resistor. If this parallel impedance were sufficiently low and therefore the current flowing in the device and to the load were sufficiently high I could see some potential for damage.

    I hope this answers your questions, and thank you for your feedback.
  • Thanks Kevin,
    Now I understand what to do with the ISET-R pin: I will just leave it open for my usage.

    My question about combining the internal and external RSET springs from the fact that it is unclear that the internal RSET is in fact disconnected by an internal switch. Having a drawing illustrating what is going on inside would have been useful here.

    You wrote that in high EMI fields, decoupling the unused ISET-R could be an option - I think one must be careful with this as it will give gain peaking in the voltage to current stage around T1/A1.

    May I add that usage of CAP1 and CAP2 are not precisely explained. I could think of :
    - What is the advantage of using the one or the other?
    - The underlying design equations to calculate the slope could maybe be a subject?
    - It says above figure 57 that adding CAP1 and CAP2 will introduce coupling of AVDD ripple into the circuit, but is that really true when terminating the capacitors at GND in stead of AVDD?
    - Are there any reason for not terminating to GND in all cases?

    Figure 61. is missing a dot.

    best regards
    Henning
  • Henning,

    Your comments regarding the switch are understood. Sometimes things like this are easy to get by us internal to TI as we're spending so much looking at the device and the internal mechanics during development that some things become obvious to us and we forget that they may not be so obvious so someone who didn't spend so much time with the part. Feedback like this is helpful.

    Your comments about the AC coupling option on the ISET-R pin are correct. In the past we've implemented this ourselves and helped other customers with EMI issues with this approach with very small capacitors without inducing any stability issues and inducing very minimal ringing.

    henning larsen said:
    May I add that usage of CAP1 and CAP2 are not precisely explained.

    In large part inclusion of these pins were driven by customer requests for compliance with other devices available on the market that implement such pins. Similarly the illustrated configurations in the datasheet are shown as they are in order to convey similar compliance with other devices. Many of your points are valid.

    henning larsen said:
    - What is the advantage of using the one or the other?

    CAP2 at least has a series resistor in front of it so you get the benefit of forming a true R/C filter while CAP1 is basically just connecting a large capacitor. Were it not for the compliance requests, just having CAP2 would most likely have been the implementation.

    henning larsen said:
    - The underlying design equations to calculate the slope could maybe be a subject?

    Off the top of my head I'm not sure what the absolute value of the series resistor in front of the CAP2 connection is, but I can look into this if you would like for help defining a better equation for the time constant of the filter(s) you might realize using CAP1 / CAP2. The on-chip resistors are good at ratiometrically matching one another, however the absolute value with vary +/-20%.

    henning larsen said:
    - It says above figure 57 that adding CAP1 and CAP2 will introduce coupling of AVDD ripple into the circuit, but is that really true when terminating the capacitors at GND in stead of AVDD? 
    - Are there any reason for not terminating to GND in all cases? 

    As I mentioned above, the illustrations too are oriented towards conveying compliance. Connecting these pins to GND would achieve the same desired filter properties as a connection to AVDD while avoiding the mentioned PSRR trade-off. It is an advisable decision if the CAP1 / CAP2 pins are used in my opinion.

  • Thanks again for the comprehensive and swift reply. With regard to CAP1, CAP2 design I have the information I need. This "strange" design with two largely redundant filters lacked a good explanation so your answer about compliance sheds light into this.

    .. and don't forget to add the dot at the next datasheet revision:-)
    br henning
  • Henning,

    Glad I could help close these issues.

    I'll keep the updates in mind for the next revision of the datasheet. I think I've just about collected enough material to merit another update to the PDS. Thanks for your comments.