Hi,
I'm using Kintex-7 FPGA to give data to DAC. So I have coded DAC interface in VHDL to give data in word-wide mode.
1 ) Data-pattern test
I did data pattern test several times by giving all 8 different patterns. Sometimes It is passing but for sometimes it is failing. But when l did data pattern test by giving all same values to all 8 data patterns, its always passing. So there is no issue with the DAC set-up or hold-time.
I probed the signals going to DAC input using chip-scope in vivado. All the signals values/timings looks as expected. I'm not able to understand the reason for this.
2) DAC input v/s output
I gave 20MHz input to DAC(Stored in FPGA ROM). I got peak at expected frequency 20MHz but so many spurious frequency components are there for single frequency input. Hence if we see the signal in time domain(using oscilloscope) shape of the signal looks little different from sine wave. None of the alarms are observed (except PLL, because I'm not using it)
Note:
- I am sending interpolated data from FPGA 16bit/SDR@160MHz by 3:1 OSERDESE
- Frame is aligned to 1st data and used for block parity. I'm using sync as single sync source for FIFO.
- Interpolation Factor : 2X
Please help me to resolve this
Thank you :)
