ADS5463 Minimum Sample Rate

Hi,

Sometimes an ADC might have phase locked loops to lock on to the clock and in that case the PLL might impose a lower limit on the clock frequency.  Other ADCs that have an LVDS DDR output may have a duty cycle correction circuit to make the input clock become 50/50 duty cycle for the output DDR clock even if the input clock is not 50/50 duty cycle, and that type of circuit also imposes a lower guaranteed sample rate.  The ADS4149 device you were using has such a duty cycle correction circuit which is why the datasheet listed 20Msps as the lower guaranteed limit.   You may find the device to operate at a lower sample rate, but the risk would be that another device from a different production lot would not work at such a low clock rate over the full range of voltage and full range of ambient temperature.  

The ADS5463 does not have a PLL nor a duty cycle correction circuit to impose a lower limit on sample rate, but there are some aspects of the design of the sample and hold circuit in the analog front end that impose the lower sample rate.  (There are internal nodes in the device that are pre-biased to a desired level and with too long of a clock period the internal node could droop too far away from the desired pre-bias before the signal is sampled.)   The ADC would operate at a lower clock rate, but the analog performance specs listed in the datasheet would no longer be guaranteed.    And since the datasheet lists 20Msps as the lower sample rate, the device was not characterized for lower speed operation so I would not be able to tell you how much performance degradation to expect either.

Regards,

Richard P.

Answer Thank you very much.

Do not you think that the ADC12D500RF product does not have a PLL circuit like the ADS5463R?

If you do not have it, it will work at clock frequency of 1Msps ~ 10Msps. Is that correct?

You do not need to guarantee perfect operation.

<corrections>



Answer Thank you very much.

Do not you think that the ADC12D500RF product does not have a PLL circuit
or sample and hold circuit in the analog front end that impose the lower sample rate like ADS 5463?

If you do not have it, it will work at lower clock frequency rather than guaranteed Specs.(20Msps)

Is that correct?

You do not need to guarantee perfect operation.

thanks

Hi,

The ADS5463 would operate below the minimum sampling rate of 20Msps, but without any guarantees of still meeting the AC performance specs, but also since the device is not production tested outside of the specified operating range I could not say how *much* below the min sampling rate you could go.   I do not know about whether as low as 1Msps is ok.

I will have to let another person speak to the ADC12D500RF.

Regards.

Richard P.

Hi

The ADC12D500RF has a minimum clock rate of 150 MHz in non-DES mode and 200 MHz in DES mode. The different lower limit for DES mode is due to the duty cycle stabilization circuitry used in that mode.

The 150 MHz limit is required to ensure that internal charge-pump circuitry operates at correctly. At lower clock rates the circuitry will not be able to supply enough current.

In addition to that limitation, the evaluation board for the ADC12D800RF/ADC12D500RF has low speed limitations due to the FPGA firmware design. These limitations will likely limit the low speed operation to some frequency above 200 MHz.

Are you designing a data acquisition system of your own, or do you intend to use an ADC evaluation board for your project? If you are designing your own system you can decimate in the FPGA to get a lower effective sample rate for storage to memory or for processing. If you need a receive bandwidth up to 5 GHz and a sample rate at 20 MSPS or below it will be tough to find an ADC evaluation board that will do exactly what you want.

I do have one other suggestion that might be worth considering. The ADC12J4000 device has a built-in decimation feature. The ADC12J4000EVM can be operated with the ADC sampling at 1000 MSPS, and with decimation of 32. This will give an complex I+Q output sample rate of 31.25 MSPS.

Best regards,

Jim B

I think that the limitation of the minimum sampling rate due to the presence of PLL circuitry or duty cycle correction circuit seems to be no problem to run in the really low sampling rate environment we want.

However, it is important to limit the minimum sampling rate in the design of the sample and hold circuit in the front end.

<Questions>
1. I'm wondering if the ADC12D500RF product you propose has a sample and hold circuit in the front end.
2. I wonder if it will not operate at the minimum sampling rate of 150Msps or less.

If you answer two questions, I would be very grateful.

Hi, Jim B

One more question.

Your recommended ADC12J4000 device.

What you mean is that the ADC12J4000 device has 32x decimation capability, which means that the minimum sampling rate of 1000Msps is 31.25Msps when decimated.

But in this case, does the bandwith also shrink?

In fact, can you briefly explain how the ADC does the data handling functions?

The ADC12D500RF cannot be operated with a clock frequency below 150 MHz.
Regards,
Jim B