We are using the DAC with interpolation and providing an external clock input at twice the JESD sample rate. We would like to use SYSREF in subclass 1 for deterministic latency among several modules. Because the internal JESD sample clock is the external clock divided by two, how can we ensure the phase of the sample clock is the same across multiple modules?
More generally, how can we get deterministic latency when using an externally generated DAC clock that is internally divided to create the JESD sample clock?
Thanks
