ADC12D1000: Test pattern in non-demux mode

Christophe Vescovi

Part Number: ADC12D1000

Hi,

I'm wondering whether the test pattern shown in table 3 of the adc12d1000 datasheet for the non-demux mode is correct.
Indeed I'm trying to synchronize my FPGA with the ADC operated at 1GHz (DCLK frequency hence is 1/2*fadc=500MHz) and I observe the following sequence for the I bus :
T0 : 004h
T1 : 004h
T2 : FFBh
T3 : FFBh
T4 : 004h
T5 : 004h
T6 : FFBh
T7 : FFBh
T8 : 004h
T9 : 004h

I'm sure that the data are sampled correctly at the FPGA input, because I perform a data phase alignment.
And I can guarantee that the data are sampled in the middle of the window.

Moreover if I compare the data I'm observing with the pattern shown in table 2 for the demux mode for the Id output,
it seems consistent with what I observe considering each sample is recorded twice.
I assume the pattern generator is located before the 1:2 demuxer, and that it is merely the same.
Thus it would make sense to see each sample of table 2 twice in the stream if the demux is not activated.

Can you confirm my observation, and if true correct the datasheet?

Thanks in advance, best regards

over 8 years ago

0 Jim Brinkhurst1 over 8 years ago

TI__Mastermind 44680 points

Hi Christophe

Can you provide the capture results in test pattern for at least 24 samples?

I believe the pattern description in the datasheet is correct for both Demux and Non-Demux modes, but will double check.

Best regards,

Jim B

0 Christophe Vescovi over 8 years ago in reply to Jim Brinkhurst1

Prodigy 20 points

Hi Jim,

Here is the captured test pattern in Non-Demux mode for I and Q (first and second column) :

4	0
4	0
4	ffff
4	ffff
fffb	0
fffb	0
4	ffff
4	ffff
fffb	0
fffb	0
4	0
4	0
4	ffff
4	ffff
fffb	0
fffb	0
4	ffff
4	ffff
fffb	0
fffb	0
4	0
4	0
4	ffff
4	ffff
fffb	0
fffb	0
4	ffff
4	ffff
fffb	0
fffb	0
4	0
4	0
4	ffff
4	ffff

Best regards,
Christophe

0 Jim Brinkhurst1 over 8 years ago in reply to Christophe Vescovi

TI__Mastermind 44680 points

Thanks Christophe

I'll try to gather some comparative data tomorrow to verify what should be happening.

Best regards,

Jim B

0 Jim Brinkhurst1 over 8 years ago in reply to Jim Brinkhurst1

TI__Mastermind 44680 points

Hi Christophe

I've verified that the non-demux test patterns for I and Q data outputs do agree with the datasheet Table.

Using the EVM it wasn't easy to get the data for I and Q simultaneously, but I was able to confirm each pattern is correct.

Here are my results. I captured using the ADC12D1XXXXRB platform which always captures assuming 1:2 demux mode. So every second data point is garbage due to the un-driven FPGA input channel.

ADC TPM captured in nondemux mode ADC12D1800RFRB.xlsx

Please look again at the configuration of your capture/clocking/storage etc. to find what can be causing issues.

Another check is to put a low frequency sine wave into the ADC. That can also help point toward what samples might be out of order, missing, duplicated, etc.

Best regards,

Jim B

0 Olivier Bourrion over 8 years ago in reply to Jim Brinkhurst1

Prodigy 10 points

Hi Jim,

Indeed we confirm that there is an issue on our side. We made another diagnostic by measuring the output signal with an oscillocope. For that we found a method to dramatically decrease the ADC sampling clock on our board. We went from 1GHz to 100 MHz (bit time of 10 ns) and we recorded DQ9_P and ORQ_P (see below) and they confirm that the datasheet is correct.

Thanks for your help.

Best regards

Olivier B.

DQ9_P capture

ORQ_P capture

0 Jim Brinkhurst1 over 8 years ago in reply to Olivier Bourrion

TI__Mastermind 44680 points

Hi Olivier
Thanks for the update.
Since you have confirmed the proper pattern at lower speed I am going to close this discussion thread.
Please post a new thread if you have any questions on other topics.
Best regards,
Jim B

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ADC12D1000: Test pattern in non-demux mode