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ADS131E08: SPI_CLK external tristate buffer is required???

Sandeep NS
Intellectual 400 points
Part Number: ADS131E08
Other Parts Discussed in Thread: ADS131E06

Hi,

I am in a design stage of a data acquisition system based on ADS131E08 ADC.

we are using multiple ADC's in parallel with CS# pin selection. From the datasheet its clear that when CS# is high SPI_Dout will be in high impedance state. So we can connect all SPI_DOUT pin in parellel. is it ok??

But for SCLK and DIN pin whether we need to use external tristate buffer?? which will be active when CS# is high or can we connect all DIN and SCLK of all ADC's in parellel?

Thanks and Regards

Sandeep

  • 0
    TI__Mastermind 38745 points
    Hello Sandeep,

    You can connect all the DOUT pins if they have separate CS pins. It's ok to connect all the DIN pins and SCLK pins as well since any commands or SCLKs will be ignored if CS is high.

    Regards,
    Brian Pisani
  • 0 in reply to Brian Pisani
    Intellectual 400 points

    Hi Brian,

    Thank you for your reply. We are usin DRDY as interrupt. 

    In the datasheet of ADS131E06 page no:21, there is a note

    When using the device in a multi-chip SPI bus configuration, a condition exists where SCLK clears DRDY even when CS is high. See
    Figure 27 for more details.

    Page no: 30

    One consideration with the SCLK signal is that the DRDY signal is cleared on the first SCLK falling edge,
    regardless of the state of CS. No data are clocked out, but the DRDY signal is cleared. This condition should be
    taken in consideration if the SPI bus is used to communicate with other devices on the same bus. Figure 27
    shows a timing diagram for this multiplexing.

    As per the above data there will be a change in DRDY regardless of CS# pin. So in our application it will act as interrupt for invalid data.

    Is my understanding is correct?

  • 0 in reply to Sandeep NS
    TI__Mastermind 38745 points
    Sandeep,

    It will change for the daisy chained devices because when you are reading from the first device, CS is high for the daisyed devices but SCLK is running. If all the devices are synchronized, the DRDY signals will all happen at the same time anyways so the DRDY signals of the daisy chained devices are extraneous. Does this make sense?

    Brian
  • 0 in reply to Brian Pisani
    Intellectual 400 points
    Hi,

    We are connecting ADC's as multiple slave devices which can be select through CS# pin. and all ADC's DRDY is connected to diffrent interrupts(Say for 4 ADC's , 4DRDY interrups are used in MCU)

    So as per datasheet its mentioned like "One consideration with the SCLK signal is that the DRDY signal is cleared on the first SCLK falling edge,
    regardless of the state of CS".

    So when I am polling from ADC1(CS1 is active and CS2,3,4 are inactive) DRDY1 interrupt will work .
    Same time is there any interrupt will come in other DRDY2,3,4 ?

    As per the datasheet statement as mentioned above it can happen even if all other ADC's will discard SCLK and DIN?

    This is my confusion?

    My requirement is i need only the interrupt from the active ADC
  • 0 in reply to Sandeep NS
    TI__Mastermind 38745 points
    Hello Sandeep,

    If you plan to monitor all DRDY pins separately, this behavior we are discussing will be an issue. This is because you will get DRDY from one device and begin reading data on that device. If the devices are not synchronized, it is possible for DRDY to not signal properly on one of the other devices because SCLK may already be toggling for the communication to the first device.

    Are you planning on synchronizing all the devices? If so, you will only need to monitor one device's DRDY pin to ensure that data is ready on all devices - thus eliminating this issue.

    Brian