DAC37J84: Eye pattern check method

Cafain,

The app note is attached.

Regards,

Jim

1462.DAC38J84 RX Tests - Eye scan.pdf

Cafain,

You can download more information regarding this from the link below.

Regards,

Jim

txn.box.com/.../jthzon8t9eookw5x8mcw6mx890nw73ac

HI, Jim-san

Please tell me how to use DAC37J84.
I am referring to the data sheet (SLASE17B).

Page 54 7.3.22 JESD 204 B Using the functions described in the Pattern Test,
How can I determine if the DAC has been successfully receiving data (whether there is no problem with SerDes transmission quality) or not,
if I tested it correctly?
The user setting conditions are
· Only use Lane0, Lane1, 9.8304Gbps/Lane
· DACCLKPN is 983.04MHz, device internal PLL unused
· Other setting values are as below
　L = 2
　M = 4
　F = 4
  S = 1
  HD = OFF
  INTERPOLATION = 4

I have a question,
Q1. Does Address: 0x64 correspond to alarm-register of Lane0 ?  also
    Does Address: 0x65 correspond to alarm-register of Lane1 ?

Q2. "1" when Bit0 of Address 0×64, 0×65 becomes Fail? (Since the default is "0")

Q3. What are the conditions for which [FIFO is empty] is "1" (Fail)?

Page28 7.3.4 Using the functions described in Serdes Equalizer,
I would like to test whether the DAC can receive data correctly (whether SerDes transmission quality is satisfactory).
I tried running as per the information described in the datasheet,
Although there is no abnormality in the result, it can not be judged whether it is executed properly.

The setting procedure is the data sheet (SLASE 17 B) page29 Step1 - Step9.
When reading register values in EQOVER and EQUNDER in Step6, the results read EQOVER= "Low", EQUNDER= "Low".

Q4. From this result, I think that there is no problem with EQ setting / operation.
    Is this okay with this idea?

Best Regards

Cafain,

Is this on a custom board or are you using a TI DAC EVM? The data sheet does have some typo's.

Q1. Address 0x64 corresponds to lane0 and add 0x65 is for lane1.

Q2. Yes, a "1" indicates an error.

Q3. The FIFO must always have data in it. If there is no data, the FIFO was emptied and data was lost, thus an error will occur. This usually is a sign that the input data is not matching the FIFO output clock rate. What FPGA family and vendor are you using? When I use your settings, the Arria V from Altera requires a 245.76MHz reference clock. What frequency are you using?

What is the frequency of your SYSREF? What value are you using for K and RBD? Can you send the DAC register settings? Do you have an option to not use the DAC PLL? This may be an easier way to get the link connected properly.

Regards,

Jim

Hi,JIm san

I checked the customer's setting conditions ·
It will be as follows

DACCLK:983.04MHz
SYSREF:61.44MHz。
K=32、RBD=31
It is assumed that DAC internal PLL is not used.

DAC3xJ8x GUI was used for register setting.
*Please ignore the LMK setting because it is unused.

---I would like to send you the configuration file, please tell me your personal e-mail address --- 

Let me ask you a question in addition

Q1.When using "7.3.22 JESD204B Pattern Test"
   Is recognition recognized as fail in Bit 0 of Address 0×64(Lane0), 0×65(Lane1) correct? .
   (What is the condition for Bit 0 to become Fail(1) in the test pattern mode?)

2.Data sheet(SLASE17B) page96 Address 0×64(Lane0), 0×65(Lane1)
　 bit1 = read_error : Asserted if read request with empty FIFO
　 bit0 = read_empty : FIFO is empty
Q2-1.
   Please explain the meaning of bit0 and bit1 (difference between both).
   As a result of confirmation by evaluation, bit0="0" and bit="1" are set.
   When FIFO is in empty state, it is thought that bit1="1" because read was executed,
   If FIFO is in empty state, we think that bit0="1".
   However, bit0="0" and bit1="1" are confirmed.
   We think that bit0="1" and bit1="1" when FIFO is empty, is it wrong?
　
Q2-2.
   bit1 = read_error : Asserted if read request with empty FIFO
   In which phase of the JESD204B interface is the phase in which bit1 error occurs?
   Is it code group synchronization (CGS), or initial lane synchronization (ILAS),
   or will it occur in the data transmission phase?

   best regards

   Cafain

Hi, Jim san

DAC3xJ8x GUI was used for register setting.

DAC3XJ8XEVM Attaches the .cfg file set in the GUI.
(Compressed with Zip)
Does this information match the file you requested?

1BF0E3C0.zip

Best regards

Cafain

Cafain,

What FPGA are you trying to interface to? Are you still not able to SYNC?

Regards,

Jim

Hi, Jim-san

FPGA is XC7Z100, XC7K325T.

SYNC has confirmed that it is outputting from DAC37J84, and the data transmission phase is
I think that it is reachable.

best regards

Cafain