I note on the data sheet in section 6.8 "Timing Requirements" that it only lists "Typical" values. We are having some issues with our design, and I want to rule out SPI timing as one possible cause. Are there in fact any values for maximum and minimum? Particularly interesting is that the Period of SCLK is given as 1uSec typical for Reg. 7, and 100nSec typical for all other registers. We are running with 100nSec for all registers, and it seems to be working. Since there is no minimum specified for Reg. 7 SCLK, is 100nSec valid? But it would be more comforting to know what the established minimum SCLK period is, and especially if this has been checked over the full temperature range. The same is true, of course, for the other timing parameters.
Extensive searching on the forum (and Googling) has not revealed any threads on this.
