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ADS1255: Device only responds when SCLK has pull down resistor

Caleb Munsill
Prodigy 40 points
Part Number: ADS1255


I am working on interfacing the ADS1255 ADC to a Xilinx's Zynq SoC using its SPI controller and am getting a weird results. I found at first that the ADC would not respond to any commands unless its SCLK line was being probed. At which point it acted and responded as expected. Upon further testing I found that running a pull-down resistor (4.7k) had the same effect. I am running the SCLK at ~475kHz and the schematic is attached below. while probing the receiving end of SCLK I don't observe any ringing and have increase the series termination resistors to as high as 1kohm with no result. Adding a pull down resistor at this point would require a full re-spin of the PCB which would be costly so I would prefer to understand why this is happening and if there is a way to fix it. Also configured and confirmed a clock phase 1 and active high clock config

Thank you in advance for any assistance you can offer.

-Caleb 

  • 0
    TI__Mastermind 44720 points

    Hi Caleb,

    First off, welcome to the TI E2E Forums!

    For my reference, what is your SCLK frequency?

    That is very odd behavior you're observing and I would not have thought to add pull-down resistor on SCLK. After thinking about it, I could only come up with two possible explanations for how the pull-down resistor may be aiding the SPI communication:

    1. A pull-down resistor may be helping to drive SCLK low.
      If for some reason your SPI controller is not driving SCLK below 0.2*DVDD, then the pull-down resistor might help achieve the logic-low state. This seems unlikely to me as I would expect the SPI controller to be able to sink sufficient current (shouldn't require much) to pull SCLK low. Otherwise, maybe the SPI controller is biased to a slightly higher ground potential and it's logic low state appears level-shifted from GND.

    2. A pull-down resistor (or scope probe) may be adding parasitic capacitance to the SCLK trace.
      Perhaps adding the probe or pull-down resistor is adding just enough parasitic capacitance to act as a filter on the SCLK trace. While increasing the series termination resistor (from 100 to 1000 Ohms) ought to have a similar effect, my guess is that the added parasitic capacitance may be  a change of more than 1 order of magnitude; hence why this was more effective than increasing the series resistance.

     

    For the later case, you might be able to resolve the communication issue by introducing some software delays. For example, I've found that adding a small delay (~50ns) between /CS low and the first SCLK rising edge can often correct communications issues. If you're able to provide some screenshots of the SPI communication, I may be able to help identify where you may be close to a timing specification and can recommend where to add delays.

    Best Regards,
    Chris