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ADS131A04: Direct measurement of load cells in a full (4x) Wheatstone bridge configuration?

Chris Carde
Prodigy 30 points
Part Number: ADS131A04
Other Parts Discussed in Thread: INA125, ADS1115, ADS131E06, INA2331

Please forgive what's probably a forehead-slapping-ly obvious question. I got thrown into this analog project and am woefully underqualified.

I'm trying to build a device to measure 6x load cell modules (with 4x load cells per module in a full Wheatstone bridge configuration) at a sampling rate of ~50 Hz. My host MCU is running the polar opposite of a real-time operating system (Android Things) and as I cannot tolerate much skew between channel samples, I want to use one of TI's simultaneous-sampling parts -- limiting my options quite a bit. Furthermore, the host cannot tolerate samples at much more than 50-100 Hz before samples dropped, further limiting my options to parts I can configure for such a low sample rate. 24 bit resolution is a bonus -- an earlier try at the intended design seemed to run into a precision-based limitation using a 16-bit part. I would have liked 50/60Hz rejection, but expect I'll just place an analog filter with a cutoff well below 50 Hz on the input side.

As it happens, the only part meeting these high-level criteria (that I could find) was the ADS131A04 (using two daisy-chained). As an aside, I'm a little worried about the datasheet being so focused on power measurement applications, but I can't see any obvious blockers for a load cell measurement application.

My core question: is it reasonable to directly connect the differential outputs of the Wheatstone bridge to the differential inputs of the ADS132A04? I plan to use a resistor divider (with high-precision resistors) to establish Vref at Vexcitation/2. I worry that the input impedance of the ADS131A04 (stated as 130k) would be low enough to affect the bridge. Is a better design to use an instrumentation amplifier with differential output? My predecessor seemed to use a single-ended instrumentation amplifier between bridge and ADC (in that case an INA125 and ADS1115), tying AINx of ADS1115 to ground. Seems like a waste of half the ADC's range to do so -- but again, I'm barely literate on the analog side. :)

Any insights appreciated!

  • 0
    TI__Mastermind 38745 points
    Hello Chris,

    You are right that the unbuffered inputs to the ADS131A04 could affect the reading of the bridge by drawing current themselves. Have you looked at using the ADS131E06? That device is a 6-channel simultaneous sampling 14-bit ADC with high impedance inputs. The only problem I see with using that device for your implementation is that the lowest sample rate is 1 kSPS. Is it possible in your system for you to ignore samples? Could you configure your processor to ignore all but one sample for every 20 DRDY signals? That would make it so you could sample at 50 SPS.

    If that device does not work, we can see if there is an op-amp or INA that could work for your system while also using the ADS131A04.

    Brian
  • 0 in reply to Brian Pisani
    Prodigy 30 points

    Thanks, Brian, for your prompt reply and useful insights.

    I actually really like the ADS131E06 as, among other things, it seems to reduce my part count: all six channels in a single package and, as you mentioned, eliminates the need for an INA. That said, the Android Things environment doesn't have any good way to ignore edges such as access to hardware counters. So, if I went this way I'd need to either add a small MCU such as MSP430 (seems like overkill) or use a discrete counter/divider part between ADS and the host processor. The discrete counter/divider isn't a terrible solution, but I'm worried I'm not seeing some subtleties with the behavior of the DRDY line. Have you seen this work, and are there any recipes I could follow to replicate it?

    In absence of a counter/divider solution, I'm still very interested in an INA/op-amp solution. If I were to copy/paste the solution from the previous design I'd be left with a single-ended output from the INA125 which -- as I mentioned -- seems a waste of the differential inputs on the ADS131A04. An INA might still be the best bet for this design as I'm not sure the PGA on the ADS131A04 is sufficient (don't have the samples of the load cell yet so can't quote full-range voltage on the bridge) and would also appreciate the ability to remove bridge offset prior to amp via software calibration.

    Your thoughts and suggestions appreciated!

  • 0 in reply to Chris Carde
    TI__Mastermind 38745 points
    Hey Chris,

    I have not seen that solution specifically implemented before, but it seems viable. To be fair, for most of the questions I answer the user has direct access to the MCU hardware peripherals which makes such behavior relatively easy to implement. I don't see any issues with using a counter to gate the DRDY, but I'd probably like to see a schematic if you do go with that solution.

    I wouldn't necessarily worry about "wasting" the dynamic range of the ADC by only potentially using half of its range. "Half" only corresponds to 1 bit out of 24. In the end, I would check to see if the noise of the INA and ADC combination has a small enough equivalent noise specification to measure the smallest signal you need to measure and then has a large enough range to measure the largest signal. This will abstract the "bits" out of consideration for whether it is the correct ADC.

    Calibration for bridge offset will probably have to happen on the software side since it will depend on the bridge and the INA.

    Brian
  • 0 in reply to Brian Pisani
    Prodigy 30 points

    HI Brian,

    Thanks again. This is tremendously helpful input.

    On the divider solution: is it typically necessary to follow the state of DRDY hroughout a read transaction, or can I trigger based solely on the edge? The latter would be necessary, I suspect, as the counter would itself be edge-triggered, obfuscating the rising edge of DRDY. I'm not convinced that's a problem, though.

    I'm not familiar with the calculations necessary to compare noise/range to ADC precision, unfortunately. But your point about 24 bits (or 23, as the case may be) being enough to not serve as the limiting factor is well taken. Given the yet-unknown need for further amplification, I'll probably stick with ADS131A04+A02 for my 6 channels. Can you recommend a suitable INA for this purpose? I had landed on INA2331 for package efficiency, but probably should be looking at more than that.

    Is three an established best practice with respect to tying AINN to GND vs VRef when using a single-ended signal on AINP? Seems that the net result is the same (half the dynamic range of the ADC), just varying the offset of the signal within that range. 

    Chris

  • 0 in reply to Chris Carde
    TI__Mastermind 38745 points
    Hey Chris,

    You could trigger this counter solely on the negative edge of DRDY since that edge is always the indicator that data is ready no matter what the state of the pin is between the edges.

    I see no issue with the INA2331. We can discuss the signal chain in more detail once you know the dynamic range of signals you'll want to measure.

    You are right about the idea of tying the pin to ground versus some other voltage like analog mid-supply. With AINxN ties to ground you limit your codes to the positive range, but again, that may not be an issue depending on your target dynamic range.

    Regards,
    Brian Pisani