DAC39J84: DAC39J84 Initialzation set up

Gerald Choi

Expert 1400 points

Part Number: DAC39J84

Hi, HighSpeed data team

We are setting Initialization set up by 135page on datasheet.

However, DAC39J84 didn't operation sync line

We checked basic status about basic hareware on power and layout and so on

Can you recommend other check point?

Best Regard

Gerald

over 8 years ago

0 Gerald Choi over 8 years ago

Expert 1400 points

Hi,
Can I get CPLD code on DAC3XJ8X EVM board?

0 jim s over 8 years ago in reply to Gerald Choi

TI__Guru* 91947 points

0451.CPLD files.zipGerald,

The code is attached.

Regards,

Jim

0 jim s over 8 years ago

TI__Guru* 91947 points

Gerald,

1. Are you using the TI EVM or is this a custom design?

2. What FPGA are you interface to?

3. What mode is the DAC setup for? This would be the LMFS settings, the "K" value, sample clock, SYSREF frequency, ect. The more info you can provide, the more we can help you.

4. Can you send the DAC register settings?

See if the attached document helps.

Regards,

Jim

6281.DAC3xJ8x Device Initialization and SYSREF Configuration.pdf

0 Gerald Choi over 8 years ago in reply to jim s

Expert 1400 points

Hi Jim

Thank you for your replay
We solved DAC39J84 sync line.

We setting DC Off on Resister for DAC output.
Can we set DC off by Hardware and Schematics?

And can we change I/Q input signal by DAC setting?

Best Regards
Gerald

0 jim s over 8 years ago in reply to Gerald Choi

TI__Guru* 91947 points

Gerald,

I am having trouble understanding your requests. Are you asking for schematics?

Please elaborate more about the DC you are talking about. Is there a DC component you are trying to remove or add?

Do you want to swap the I and Q digital data coming into the part?

Regards,

Jim

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DAC39J84: DAC39J84 Initialzation set up