Dear all,
I am designing a data acquisition system based on the ADS1274 which is a 24 bits, 4 channels, up to 144 kS/s ADC.
My requirements are the follwing:
- I need the 4 channels
- The sampling frequency will be 128 KHz (128 kS/s)
After reading the datasheet, I have the choice between 2 communication interfaces: SPI or Frame-Sync Interface
Due to the speed requirement, I do need to use the "high-speed mode". It would be good to use the SPI because my microcontroller (FX3 from Cypress) is ready to use SPI directly up to 33 MHz. SPI with ADS1274 can run up to 27 MHz according to the datasheet. So I made calculation:
4 channels * 24 bits * 128000 samples / s = 12'288'000 bits/s which is okay according to the 27 MHz (if I transfert 1 bit / cycle).
But... I saw 2 weird things in the datasheet http://www.ti.com/lit/ds/symlink/ads1274.pdf :
- page 8/51: tconv (the time to aquire 24 bits of the 4 channels) is 256 clock cycles minimum with SPI. I do not understand, why is it not 96 clock cycles ? 4 channels * 24 bits = 96.
- page 30/51: SPI can run up to 27 MHz which is okay but... page 3/51: 27 MHz can transfert up to 105'461 S/s and I need 32.768 MHz to get 128 kS/s...
According to these facts, it means that during a "transfert" of 256 clock cycles, the SPI can tranfert only during 96 clock cycles and the interface is idle during 160 clock cycles? If I make a new calculation:
256/96 (ratio of total clock cycles and "transfert clock cycles") * 4 channels * 24 bits * 128'000 samples / s = 32.768 MHz which matchs perfectly with the information in the datasheet.
Finally, my questions are the following:
- Do I need to use the Sync-frame interface in my case ?
- Why are there 160 'idle' clock cycles during a tranfert of 256 clock cycles?
Sorry for the long post,
Best,
Christian
