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ADC10065: Problem for the first conversion

Satoshi
Guru 19685 points

Part Number: ADC10065

Customer is using ADC10065, but the first conversion is abnormal.

Waveform is attached below, please let me know about possible cause.

【Other specs】　

・VDDA： 3.3V

・VDDIO： 2.5V

・Clock frequency： 53.3MHz

・Single end input

Best regards,

Satoshi

  • 0
    TI__Mastermind 44680 points

    Hi Satoshi

    Based on the information provided I'm not sure the cause of the glitch seen in the first few samples.

    Can you provide the schematic including the entire signal path and all ADC connections? Does the signal source have the same output impedance in both cases shown above?

    How long before Sample 1 are the ADC power supply voltages stable?

    How long before Sample 1 is the ADC CLK running and stable?

    Is the input signal stable for some period of time before Sample 1? How long?

    Best regards,

    Jim B

  • 0 in reply to Jim Brinkhurst1
    Guru 19685 points

    Jim-san

    Thank you for reply,

    I answered your question,

    -------------------------------------

    ・Can you provide the schematic including the entire signal path and all ADC connections? Does the signal source have the same output impedance in both cases shown above?

    　⇒Schematic is attached below.

    ADC10065.pdf

    ・How long before Sample 1 are the ADC power supply voltages stable?

    　How long before Sample 1 is the ADC CLK running and stable?

    　⇒I confirming timing, but these are stable.

    　　And, Clock is Fixed low before ADC start.

    ・Is the input signal stable for some period of time before Sample 1? How long?

    　⇒Yes, Sample 1 is only unstable.

    -------------------------------------

    Sorry for additional question, please let me know about two points below.

    ①Customer is considering that ADC data take in Sample 8～, is it correct?

    ②Datasheet page 18 is descrimbed below.

    　"If the CLK is interrupted, or its frequency is too low, the charge on internal capacitors can dissipate to the point where the accuracy of the output data will degrade.

    　 This is what limits the lowest sample rate. The duty cycle of the clock signal can affect the performance of any A/D Converter."

    ⇒When ADC CLK is fixed low before ADC start, is ADC accuracy degrade for a few Sample beginning?

    ※Reference data is attached.

    USS44SH Transmit Test_20150216Naka.xlsx

    Best regards,

    Satoshi

  • 0 in reply to Satoshi
    TI__Mastermind 44680 points

    Hi Satoshi

    I think the customer is on the right track regarding the cause of the issue.

    If they are holding the clock at logic low and then starting it up just before they want to get valid data, the ADC performance won't be optimal right away. It will take some time for the ADC circuitry to stabilize after CLK is started. I would recommend starting the ADC clock some time before they want to start using the data. This will ensure the ADC is stable and providing the proper performance. They can experiment with what works, and then add a few more clock cycles to ensure there is some margin for device to device variation.

    Best regards,

    Jim B

  • 0 in reply to Jim Brinkhurst1
    Guru 19685 points
    Jim-san

    Thank you for advice.
    I think that this issue is depend on input clock source, and ADC10065 is not related this issue.
    Is it correct?

    By the way, input clock source is FPGA (Arria 10).

    Best regards,
    Satoshi
  • 0 in reply to Satoshi
    TI__Mastermind 44680 points
    Hi Satoshi
    I agree the issue is not caused by a problem with the ADC10065, but how they are using it with a discontinuous clock.
    Best regards,
    Jim B