ADC32RF45: adc input clock jitter and performance

Hello

here some feedback regarding your questions.

1) The integration bandwidth depends on a couple of different factors:

- Application: if your application is dealing with modulated signals occupying a specific bandwidth and channel spacing that this sets your practical lower integration limit (in case of a full power interferer occupying one channel)

- Test case: if you perform FFT processing, then the FFT size sets your lower end limit. For example 3Gsps output rate with a 65k FFT yields in a lower integration limit of ~ 24kHz (3e9/65536 / 2)

The upper integration limit can be set by several different factors as well:

- bandwidth an external clock filter

- input bandwidth of the clock input buffer inside the ADC

- worst case integration limit would be 2x the sampling rate.

Here some additional reading material on that matter:

www.ti.com/lit/an/slyt379/slyt379.pdf

www.ti.com/lit/an/slyt389/slyt389.pdf

Regarding #2:

the SNR in dBc depends on the input signal voltage. For example the ADC32RF45 has a thermal noise floor of ~ 63dBFS. If your input signal is a sinewave with -2dBFS amplitude then the thermal noise would be 63dBFS or 61dBc

Regarding #3:

Similar as #2. However quantization noise is rarely a factor with highspeed converters. To get final SNR number you have to add thermal, quantization and clock noise. Thermal noise on RF45 is ~ 63dBFS. Quantization noise at 12bit output ~ 74dB and ~ 86dB with 14bit. Even at 12bit output quantization noise is ~ 11dB lower than thermal noise and degrades overall SNR very minimal. In fact going from 14bit to 12bit output the SNR degrades ~ 0.1dB.

here some additional reading material. It should be pointed out that the clock amplitude also has a large impact on the SNR performance of the ADC.

http://www.ti.com/lit/an/slyt705/slyt705.pdf