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ADS1271: CLK Specifications

Richard Elmquist
Mastermind 45250 points
Part Number: ADS1271

I have a customer who has some questions about the CLK input. The data sheet states that you should use a high-quality low-jitter clock source as this clock controls the operation of the entire chip. But it does not give any details. Please look at the customer’s issue below:

 I would like more detail about the requirements for the main clock that has to be supplied to the ADS1271. Specifically, does the duty cycle of the clock matter (does it need to be 50%)? Does it only require evenly space rising edges, or do the falling edges need to be precise and consistent as well? Due to a design mistake, I find myself unable to synthesize the exact main clock frequency required for my chosen SPS. I may be able to make one with a different duty cycle, though.

I did not know how to answer this as there are no duty-cycle limits listed in the data sheet and there is not an explanation of how the ADS1271 uses the rising or falling edge internally. Can you comment on these questions.

Thanks for your help with this!

Richard Elmquist

  • 0
    TI__Mastermind 45250 points

    Here is an additional comment from the customer:

    We would like to know if a duty cycle of either 51.1% or 48.9% would be acceptable. The clock is divided down from a high-quality low-jitter source, we are just not able to divide it to have a 50% duty cycle.

    Thanks for your help with this!

    Richard Elmquist

  • 0 in reply to Richard Elmquist
    TI__Mastermind 45250 points

    Has anyone had a chance to look at the request above?

    Can you give a time frame as to when you might be able to provide the information?

    Thanks for your help with this!

    Richard Elmquist

  • 0 in reply to Richard Elmquist
    TI__Guru 66466 points
    Hi Richard,

    Please excuse my delay. I'm still trying to verify the CLK duty cycle requirement with the designer.

    In the meantime, do you know which interface format the customer is using for the ADS1271? I'm trying to determine if there are any important relationships between the CLK rising/falling edges and the interface signals.

    Best Regards,
  • 0 in reply to Ryan Andrews
    TI__Mastermind 45250 points

    Ryan,

    This is referring to the master clock. Do the specifications change for the master clock depending on their interface?

    I will see what I can find out from the customer? I will reply back as soon as I hear from them.

    Thanks for your help with this!

    Richard Elmquist

  • 0 in reply to Richard Elmquist
    TI__Guru 66466 points

    Hi Richard,

    The reason I asked about the interface was because there are some timing specs between the master clock (CLK) and the interface signals ("tCD" in SPI format, "tCF" in Frame-Sync format).

    More importantly, I can tell you that there is not a fixed duty cycle requirement for the ADS1271. Instead, we specify a minimum pulse width ("tCPW") of 15ns for both interface formats. Depending on the CLK frequency, tCPW sets the duty cycle requirement. The duty cycle of CLK will not affect analog performance since the modulator runs off of a divided version of CLK (either CLK/2, CLK/4, or CLK/8 depending on the MODE).

    Best Regards,

  • 0 in reply to Ryan Andrews
    TI__Mastermind 45250 points

    Ryan,

    Thanks so much!

    I will let you know if the customer has any further questions.

    Have a great day.

    Richard Elmquist

  • 0 in reply to Richard Elmquist
    TI__Mastermind 45250 points

    Ryan,

    The customer has asked if the dividing circuit is based on the rising or falling edge. I am not sure why they are asking this, but they wanted to know whether this is a rising edge circuit or a falling edge circuit. I would think rising edge, but I wanted to verify this with you.

    Thanks for your help with this!

    Richard Elmquist

  • 0 in reply to Richard Elmquist
    TI__Guru 66466 points

    Hi Richard,

    This question does not make much sense to me either. The edge used for sampling may vary among our devices, but the period will not be affected by the duty cycle of the incoming master CLK after it is divided down. I've asked the designer just in case there is a particular edge-to-edge relationship that should be kept constant.

    Best Regards,

  • 0 in reply to Ryan Andrews
    TI__Mastermind 45250 points

    Ryan,

    I believe that the ADS1271 uses the rising edge as the trigger for all of the circuits that it controls. Would this be correct? I understand that it would not seem to be important, but it may be that their clock has a varying rising edge and they might be worried that this would affect the operation. From your comments I do not believe that this is the case, but I just wanted to make sure that there would be no issues.

    Thanks for your help with this!

    Richard Elmquist

  • 0 in reply to Richard Elmquist
    TI__Guru 66466 points

    Hi Richard,

    I just received confirmation from the designers. The modulator clock is derived from the rising edge of CLK. Therefore, it is important to keep the rising edge -> rising edge relationship constant.

    The rising edge of the modulator clock determines when the input signal is sampled by the modulator. If the variation in the rising edge has a Gaussian distribution, then I believe the main impact will be a reduction in SNR performance, similar to clock jitter. The benefit of delta-sigma ADCs is that the oversampling architecture minimizes the impact of clock jitter, so this may help as well. If the variation is not Gaussian, I cannot say for sure what the impact will be.

    Best Regards,

  • 0 in reply to Ryan Andrews
    TI__Mastermind 45250 points

    Ryan,

    Thanks for your response!

    I will let you know if the customer has any further questions.

    Thanks again.

    Richard Elmquist