Custom ADS1298 implementation with excellent grounding and powering, produces very low noise Lead I and Lead II signals using Ch 3 & Ch 4. V1-V6 use the internally generated WCT node (with the required 100pF cap), and these exhibit a 100 Hz triangle noise artifact. The WCT is generated by setting Reg 18 to 0x0C and Reg 19 to 0xEE. This is intended to sum the RA, LA, & LL electrodes to form WCT. The system is acquiring at 500sps, is in low-power mode, and the WCT_CHOP bit in Reg 02 is 0.
This configuration utilizes the internal 2.048MHz clock, which is known from experience to be slightly inaccurate. However, the peaks and valleys of this 100Hz triangle noise appear to be very regular, suggesting that the sample times and the noise are synchronous, i.e., the noise source is somehow related to the sampling frequency of the ADS1298.
This is the NFBGA package, passive external networks are implemented with 0402 & 0603 sized components, assembly done on both primary and secondary board sides.
