Because of the holidays, TI E2E™ design support forum responses will be delayed from Dec. 25 through Jan. 2. Thank you for your patience.

  • State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 45 subscribers
  • Views 393 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS8507: Question of Intermediate Latches for the ADS8507

Wayne Chen (Audio AE)
Genius 15950 points
Part Number: ADS8507

Hi Sirs,

The ADS8507 datasheet suggests intermediate latches as the picture below. Would you pls advise the reference schematic of the intermediate latches or application note to address detail picture of it?



Thank you and Best regards,

Wayne Chen
02/24/2017

  • 0
    TI__Mastermind 39545 points
    Hello Wayne,
    Unfortunately, we do not have application note for this. The suggestion is just for special situation,the bus is active during ADC's conversion and large transients from fast switching signals on the parallel port, because it is possible that the transients are coupled through the substrate to the analog circuitry when ADC is working on the data conversions which is critical for the performance. If your circuit does not have these conditions, you do not need to worry, but It's always a good practice for the customers to monitor /BUSY signal from their controller device, disable the bus when ADC is in conversion phase, read the data when detecting /BUSY high. Another possible solution is, a digital bus buffer(245 or 16245 logic) with enable/disable function can be used between ADC and controller, and make sure the buffer is only enabled to retrieve the conversion data. I hope this can answer your question. Thanks.

    Best regards
    Dale Li