TSW1400EVM: logical analysis，tsw1400 data collection

Hi,

I'm sorry, I don't see what the question is.   Could you please explain?  If you want to see what the TSW1400 could do for you in your analysis of an ADC EVM such as the one you mention, you could consult the User Guide that is on the TI web for the TSW1400 and the HSDCPro - which is the GUI for the TSW1400.   This would tell you much about what the TSW1400 and HSDCPro GUI is capable of doing for you.

Thanks,

Richard P.

Thank you for your reply
I would like to use my own works on the work generated by quartus ads54rf63 control. Can you give suggestions? I have used the quartus generated. Rbf file lit up the led lights

Hi,

I still do not understand what you are asking for.    You are trying to edit the FPGA firmware in the TSW1400 to do something of your own design?  And are having trouble with the ADC interface?    The source code for the TSW1400 is written to handle a number of different ADC types, and there are registers that are written to the firmware to set it up for one EVM or another EVM.  The HSDCPro installation has a folder of ini files that include settings in the firmware for different EVMs.   Looking at the ini file for the ADS54RF63 I see these lines in the ini file:

check_fclk=0
srf=1
df=1
adc_type=0
adc_check=0
Max sample Rate=500000000
fclk_code=0
config1=24
config6=0
config7=0

if you recompile the source code to do something else and you don't also still set the registers that need to be set for ADS54RF63 according to how the HSDCPro sets them using these ini file parameters, then the firmware will behave differently.  Maybe this is an issue for you.

Regards,

Richard P.

hi

i have a  problem about adc interface.

i want to know the FCLK_M(P) means what,because i check the ads54rf63 datesheet  , the FCLK means  MSB_6 (Adc data output bit), and i check a example from TI , it also dont used for adc.

can you give me an advice about Adc and tsw1400 interface at the key definition, especially msb_6 (an adc data output pin)

Hi,

The names attached to the connector pins on the different schematics are nothing more than just names.   Our TSW1400 capture card supports many different EVMs, and some EVMs are one channel, others two or more channels, and anywhere from 8 to 16 bits each.   There is no single name that we could put on a connector pin that would be the 'correct' name for every EVM.    What you would have to do is follow the schematics for the EVM from all of the LVDS outputs to the connector pins that they connect to.  And then follow the same connector pins up to the FPGA on the capture card to get for yourself a mapping on which FPGA pins connect to which ADC pins.  Then you would use these FPGA pins in the constraint file for your FPGA code to assign these LVDS signals to those FPGA pins. 

On some EVMs that pair of connector pins might be bit 5 of a 12 bit bus in the case of ADS5463, or it might be bit 7 of a 14bit bus in the case of ADS5474.   Or on some of our other EVMs such as ADS5282 that pair of connector pins might be called FCLK or Frame Clock.    Regardless of the name, once you plug a specific EVM into the connector then the FPGA firmware has to use it in the proper manner for the EVM that you have plugged in at that  time.

Regards,

Richard P.

Hi,

you can use any FPGA board you wish, but you will still have to trace out all the schematics to find out which FPGA pins will be receiving the signals from the ADC EVM, and write your FPGA firmware accordingly.  You will also have to check with the FPGA datasheet to make sure that the FPGA pins are capable of receiving the LVDS signals at the desired data rate, and that the FPGA pins that the clock signal goes to is capable of accepting a clock input.   The ADS54RF63 does not have any programmable registers so there is no configuration needed to be done to the ADC - the FPGA firmware would just have to be written to properly accept the data format that the ADC outputs. 

Regards,

Richard P.

Hi,

i would not recommend using a clock from an FPGA as a sample clock for an ADC.  The clock would likely have too much jitter on it to provide for good performance in achieving the SNR that the data converter is capable of.    The datasheet for the ADC will have a typical specification for clock amplitude, but often there would not be a minimum amplitude specified.  There will usually be a plot of SNR and SFDR as a function of clock amplitude that shows how the AC performance begins to decrease at lower clock amplitudes, allowing the user to choose their own appropriate minimum specification based on how much they can tolerate a loss of performance.   For example, in the ADS5463 datasheet the figures 59 and 60 are an example of this kind of plot of performance over clock amplitude.

Regards,

Richard P.