• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 46 subscribers
  • Views 618 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

vertical line appear at the right side of display when input YCbCr, 20bits, 4:2:2 with embedded sync to THS8200

Joe Lam
Prodigy 40 points
Other Parts Discussed in Thread: THS8200, TVP7002

 I have a question on the THS8200 running in VESA slave mode with input of 20bits, YCbCr, 4:2:2, and embedded sync.  I am using the color base converter on THS8200 to convert YCbCr embedded sync digital video to RGBHV output.  The output video shows vertical lines at the rightmost of the screen.  I used the eval board and found the eval board also has these vertical lines.  I adjust the position of the EAV at the TVP7002 and the line moves so the THS8200 is also encode the EAV data from the embedded sync.  The DM6467 VPIF display port output video with embedded sync only so the input to THS8200 is limited with this input format.  I attached the eval board registers setting in 800x600 VGA input so you can see the line on the eval board output.  Is there any settings in the THS8200 to avoid encode of the EAV data? 

BEGIN_DATASET  // Replaced by WinVCC v5.24.  Saved all registers.

DATASET_NAME,"800x600 VGA with YCbCr, 4:2:2, embedded sync, 20bits output"


WR_REG,THS8200,0x01,0x03,0xC1 // chip_ctl           
WR_REG,THS8200,0x01,0x04,0x81 // csc_ric1           
WR_REG,THS8200,0x01,0x05,0xD5 // csc_rfc1           
WR_REG,THS8200,0x01,0x06,0x00 // csc_ric2           
WR_REG,THS8200,0x01,0x07,0x00 // csc_rfc2           
WR_REG,THS8200,0x01,0x08,0x06 // csc_ric3           
WR_REG,THS8200,0x01,0x09,0x29 // csc_rfc3           
WR_REG,THS8200,0x01,0x0A,0x04 // csc_gic1           
WR_REG,THS8200,0x01,0x0B,0x00 // csc_gfc1           
WR_REG,THS8200,0x01,0x0C,0x04 // csc_gic2           
WR_REG,THS8200,0x01,0x0D,0x00 // csc_gfc2           
WR_REG,THS8200,0x01,0x0E,0x04 // csc_gic3           
WR_REG,THS8200,0x01,0x0F,0x00 // csc_gfc3           
WR_REG,THS8200,0x01,0x10,0x80 // csc_bic1           
WR_REG,THS8200,0x01,0x11,0xBB // csc_bfc1           
WR_REG,THS8200,0x01,0x12,0x07 // csc_bic2           
WR_REG,THS8200,0x01,0x13,0x42 // csc_bfc2           
WR_REG,THS8200,0x01,0x14,0x00 // csc_bic3           
WR_REG,THS8200,0x01,0x15,0x00 // csc_bfc3           
WR_REG,THS8200,0x01,0x16,0x14 // csc_offset1        
WR_REG,THS8200,0x01,0x17,0xAE // csc_offset12       
WR_REG,THS8200,0x01,0x18,0x8B // csc_offset23       
WR_REG,THS8200,0x01,0x19,0x15 // csc_offset3        
WR_REG,THS8200,0x01,0x1A,0x00 // tst_cntl           
WR_REG,THS8200,0x01,0x1B,0x00 // tst_ramp_cntl      
WR_REG,THS8200,0x01,0x1C,0x73 // dman_cntl          
WR_REG,THS8200,0x01,0x1D,0x00 // dtg_y_sync1        
WR_REG,THS8200,0x01,0x1E,0x00 // dtg_y_sync2        
WR_REG,THS8200,0x01,0x1F,0x00 // dtg_y_sync3        
WR_REG,THS8200,0x01,0x20,0x00 // dtg_cbcr_sync1     
WR_REG,THS8200,0x01,0x21,0x00 // dtg_cbcr_sync2     
WR_REG,THS8200,0x01,0x22,0x00 // dtg_cbcr_sync3     
WR_REG,THS8200,0x01,0x23,0x23 // dtg_y_sync_upper   
WR_REG,THS8200,0x01,0x24,0x23 // dtg_cbcr_sync_upper
WR_REG,THS8200,0x01,0x25,0x37 // dtg_spec_a         
WR_REG,THS8200,0x01,0x26,0x58 // dtg_spec_b         
WR_REG,THS8200,0x01,0x27,0x2C // dtg_spec_c         
WR_REG,THS8200,0x01,0x28,0x84 // dtg_spec_d         
WR_REG,THS8200,0x01,0x29,0x00 // dtg_spec_d1        
WR_REG,THS8200,0x01,0x2A,0xC3 // dtg_spec_e         
WR_REG,THS8200,0x01,0x2B,0x00 // dtg_spec_h_msb     
WR_REG,THS8200,0x01,0x2C,0x00 // dtg_spec_h_lsb     
WR_REG,THS8200,0x01,0x2D,0x00 // dtg_spec_i_msb     
WR_REG,THS8200,0x01,0x2E,0x00 // dtg_spec_i_lsb     
WR_REG,THS8200,0x01,0x2F,0x62 // dtg_spec_k_lsb     
WR_REG,THS8200,0x01,0x30,0x00 // dtg_spec_k_msb     
WR_REG,THS8200,0x01,0x31,0x00 // dtg_spec_k1        
WR_REG,THS8200,0x01,0x32,0x58 // dtg_speg_g_lsb     
WR_REG,THS8200,0x01,0x33,0x00 // dtg_speg_g_msb     
WR_REG,THS8200,0x01,0x34,0x04 // dtg_total_pixel_msb
WR_REG,THS8200,0x01,0x35,0x20 // dtg_total_pixel_lsb
WR_REG,THS8200,0x01,0x36,0x80 // dtg_linecnt_msb    
WR_REG,THS8200,0x01,0x37,0x01 // dtg_linecnt_lsb    
WR_REG,THS8200,0x01,0x38,0x87 // dtg_mode           
WR_REG,THS8200,0x01,0x39,0x22 // dtg_frame_field_msb
WR_REG,THS8200,0x01,0x3A,0x74 // dtg_frame_size_lsb 
WR_REG,THS8200,0x01,0x3B,0x74 // dtg_field_size_lsb 
WR_REG,THS8200,0x01,0x3C,0x80 // dtg_vesa_cbar_size 
WR_REG,THS8200,0x01,0x3D,0x00 // dac_upper          
WR_REG,THS8200,0x01,0x3E,0x00 // dac1_test          
WR_REG,THS8200,0x01,0x3F,0x00 // dac2_test          
WR_REG,THS8200,0x01,0x40,0x00 // dac3_test          
WR_REG,THS8200,0x01,0x41,0x40 // csm_clip_gy_low    
WR_REG,THS8200,0x01,0x42,0x40 // csm_clip_bcb_low   
WR_REG,THS8200,0x01,0x43,0x40 // csm_clip_rcr_low   
WR_REG,THS8200,0x01,0x44,0x53 // csm_clip_gy_high   
WR_REG,THS8200,0x01,0x45,0x3F // csm_clip_bcb_high  
WR_REG,THS8200,0x01,0x46,0x3F // csm_clip_rcr_high  
WR_REG,THS8200,0x01,0x47,0x40 // csm_shift_gy       
WR_REG,THS8200,0x01,0x48,0x40 // csm_shift_bcb      
WR_REG,THS8200,0x01,0x49,0x40 // csm_shift_rcr      
WR_REG,THS8200,0x01,0x4A,0x8C // csm_mult_gy_msb    
WR_REG,THS8200,0x01,0x4B,0x44 // csm_mult_bcb_rcr_msb
WR_REG,THS8200,0x01,0x4C,0x00 // csm_mult_gy_lsb    
WR_REG,THS8200,0x01,0x4D,0x00 // csm_mult_bcb_lsb   
WR_REG,THS8200,0x01,0x4E,0x00 // csm_mult_rcr_lsb   
WR_REG,THS8200,0x01,0x4F,0xC0 // csm_mode           
WR_REG,THS8200,0x01,0x50,0x00 // dtg_bp1_2_msb      
WR_REG,THS8200,0x01,0x51,0x00 // dtg_bp3_4_msb      
WR_REG,THS8200,0x01,0x52,0x00 // dtg_bp5_6_msb      
WR_REG,THS8200,0x01,0x53,0x00 // dtg_bp7_8_msb      
WR_REG,THS8200,0x01,0x54,0x00 // dtg_bp9_10_msb     
WR_REG,THS8200,0x01,0x55,0x00 // dtg_bp11_12_msb    
WR_REG,THS8200,0x01,0x56,0x00 // dtg_bp13_14_msb    
WR_REG,THS8200,0x01,0x57,0x00 // dtg_bp15_16_msb    
WR_REG,THS8200,0x01,0x58,0x00 // dtg_bp1_lsb        
WR_REG,THS8200,0x01,0x59,0x00 // dtg_bp2_lsb        
WR_REG,THS8200,0x01,0x5A,0x00 // dtg_bp3_lsb        
WR_REG,THS8200,0x01,0x5B,0x00 // dtg_bp4_lsb        
WR_REG,THS8200,0x01,0x5C,0x00 // dtg_bp5_lsb        
WR_REG,THS8200,0x01,0x5D,0x00 // dtg_bp6_lsb        
WR_REG,THS8200,0x01,0x5E,0x00 // dtg_bp7_lsb        
WR_REG,THS8200,0x01,0x5F,0x00 // dtg_bp8_lsb        
WR_REG,THS8200,0x01,0x60,0x00 // dtg_bp9_lsb        
WR_REG,THS8200,0x01,0x61,0x00 // dtg_bp10_lsb       
WR_REG,THS8200,0x01,0x62,0x00 // dtg_bp11_lsb       
WR_REG,THS8200,0x01,0x63,0x00 // dtg_bp12_lsb       
WR_REG,THS8200,0x01,0x64,0x00 // dtg_bp13_lsb       
WR_REG,THS8200,0x01,0x65,0x00 // dtg_bp14_lsb       
WR_REG,THS8200,0x01,0x66,0x00 // dtg_bp15_lsb       
WR_REG,THS8200,0x01,0x67,0x00 // dtg_bp16_lsb       
WR_REG,THS8200,0x01,0x68,0x00 // dtg_linetype1      
WR_REG,THS8200,0x01,0x69,0x00 // dtg_linetype2      
WR_REG,THS8200,0x01,0x6A,0x00 // dtg_linetype3      
WR_REG,THS8200,0x01,0x6B,0x00 // dtg_linetype4      
WR_REG,THS8200,0x01,0x6C,0x00 // dtg_linetype5      
WR_REG,THS8200,0x01,0x6D,0x00 // dtg_linetype6      
WR_REG,THS8200,0x01,0x6E,0x00 // dtg_linetype7      
WR_REG,THS8200,0x01,0x6F,0x00 // dtg_linetype8      
WR_REG,THS8200,0x01,0x70,0x80 // dtg_hlength_lsb    
WR_REG,THS8200,0x01,0x71,0x00 // dtg_hdly_msb       
WR_REG,THS8200,0x01,0x72,0x01 // dtg_hdly_lsb       
WR_REG,THS8200,0x01,0x73,0x05 // dtg_vlength_lsb    
WR_REG,THS8200,0x01,0x74,0x00 // dtg_vdly_msb       
WR_REG,THS8200,0x01,0x75,0x01 // dtg_vdly_lsb       
WR_REG,THS8200,0x01,0x76,0x00 // dtg_vlength2_lsb   
WR_REG,THS8200,0x01,0x77,0x07 // dtg_vdly2_msb      
WR_REG,THS8200,0x01,0x78,0xFF // dtg_vdly2_lsb      
WR_REG,THS8200,0x01,0x79,0x00 // dtg_hs_in_dly_msb  
WR_REG,THS8200,0x01,0x7A,0x00 // dtg_hs_in_dly_lsb  
WR_REG,THS8200,0x01,0x7B,0x00 // dtg_vs_in_dly_msb  
WR_REG,THS8200,0x01,0x7C,0x00 // dtg_vs_in_dly_lsb  
WR_REG,THS8200,0x01,0x82,0x7B // pol_cntl           
WR_REG,THS8200,0x01,0x83,0x00 // cgms_header        
WR_REG,THS8200,0x01,0x84,0x00 // cgms_payload_msb   
WR_REG,THS8200,0x01,0x85,0x00 // cgms_payload_lsb   

WR_REG,TVP7000,0x01,0x01,0x42 // H-PLL FEEDBACK DIVIDER MSB 
WR_REG,TVP7000,0x01,0x02,0x00 // H-PLL FEEDBACK DIVIDER LSB 
WR_REG,TVP7000,0x01,0x03,0x58 // H-PLL CONTROL              
WR_REG,TVP7000,0x01,0x04,0x80 // H-PLL PHASE SELECT         
WR_REG,TVP7000,0x01,0x05,0x06 // CLAMP START                
WR_REG,TVP7000,0x01,0x06,0x10 // CLAMP WIDTH                
WR_REG,TVP7000,0x01,0x07,0x60 // HSOUT OUTPUT WIDTH         
WR_REG,TVP7000,0x01,0x08,0x3C // BLU FINE GAIN           
WR_REG,TVP7000,0x01,0x09,0x3C // GRN FINE GAIN           
WR_REG,TVP7000,0x01,0x0A,0x3C // RED FINE GAIN           
WR_REG,TVP7000,0x01,0x0B,0x80 // BLU FINE OFFSET         
WR_REG,TVP7000,0x01,0x0C,0x80 // GRN FINE OFFSET         
WR_REG,TVP7000,0x01,0x0D,0x80 // RED FINE OFFSET         
WR_REG,TVP7000,0x01,0x0E,0x24 // SYNC CONTROL 1             
WR_REG,TVP7000,0x01,0x0F,0x22 // H-PLL AND CLAMP CONTROL    
WR_REG,TVP7000,0x01,0x10,0x58 // SYNC ON GREEN THRESHOLD    
WR_REG,TVP7000,0x01,0x11,0x40 // SYNC SEPERATOR THRESHOLD   
WR_REG,TVP7000,0x01,0x12,0x01 // H-PLL PRE-COAST            
WR_REG,TVP7000,0x01,0x13,0x00 // H-PLL POST-COAST           
WR_REG,TVP7000,0x01,0x15,0x43 // OUTPUT FORMATTER           
WR_REG,TVP7000,0x01,0x16,0x11 // MISC CONTROL 1             
WR_REG,TVP7000,0x01,0x17,0x02 // MISC CONTROL 2             
WR_REG,TVP7000,0x01,0x18,0x11 // MISC CONTROL 3             
WR_REG,TVP7000,0x01,0x19,0xAA // INPUT MUX SELECT 1         
WR_REG,TVP7000,0x01,0x1A,0xCA // INPUT MUX SELECT 2         
WR_REG,TVP7000,0x01,0x1B,0x77 // BLU AND GRN COARSE GAIN 
WR_REG,TVP7000,0x01,0x1C,0x07 // RED COARSE GAIN         
WR_REG,TVP7000,0x01,0x1D,0x00 // FINE OFFSET LSB            
WR_REG,TVP7000,0x01,0x1E,0x10 // BLU COARSE OFFSET       
WR_REG,TVP7000,0x01,0x1F,0x10 // GRN COARSE OFFSET       
WR_REG,TVP7000,0x01,0x20,0x10 // RED COARSE OFFSET       
WR_REG,TVP7000,0x01,0x21,0x0D // HSOUT OUTPUT START         
WR_REG,TVP7000,0x01,0x22,0x00 // MISC CONTROL 4             
WR_REG,TVP7000,0x01,0x26,0x80 // AUTO LEVEL CONTROL ENABLE  
WR_REG,TVP7000,0x01,0x28,0x53 // AUTO LEVEL CONTROL FILTER  
WR_REG,TVP7000,0x01,0x29,0x08 // RESERVED               
WR_REG,TVP7000,0x01,0x2A,0x83 // FINE CLAMP CONTROL         
WR_REG,TVP7000,0x01,0x2B,0x00 // POWER CONTROL              
WR_REG,TVP7000,0x01,0x2C,0x50 // ADC SETUP                  
WR_REG,TVP7000,0x01,0x2D,0x00 // COARSE CLAMP CONTROL       
WR_REG,TVP7000,0x01,0x2E,0x80 // SOG CLAMP CONTROL          
WR_REG,TVP7000,0x01,0x2F,0x0C // RGB COARSE CLAMP CONTROL   
WR_REG,TVP7000,0x01,0x30,0x04 // SOG COARSE CLAMP CONTROL   
WR_REG,TVP7000,0x01,0x31,0x18 // AUTO LEVEL CONTROL PLACEMENT
WR_REG,TVP7000,0x01,0x34,0x03 // MACROVISION STRIPPER WIDTH 
WR_REG,TVP7000,0x01,0x35,0x00 // VSYNC ALIGNMENT            
WR_REG,TVP7000,0x01,0x36,0x00 // SYNC BYPASS                
WR_REG,TVP7000,0x01,0x3D,0x06 // LINE LENGTH TOLERANCE      
WR_REG,TVP7000,0x01,0x3F,0x00 // VIDEO BANDWIDTH CONTROL    
WR_REG,TVP7000,0x01,0x40,0xE3 // AVID START PIXEL LSB       
WR_REG,TVP7000,0x01,0x41,0x00 // AVID START PIXEL MSB       
WR_REG,TVP7000,0x01,0x42,0x03 // AVID STOP PIXEL LSB        
WR_REG,TVP7000,0x01,0x43,0x04 // AVID STOP PIXEL MSB        
WR_REG,TVP7000,0x01,0x44,0x01 // VBLK START LINE OFFSET (F0)
WR_REG,TVP7000,0x01,0x45,0x01 // VBLK START LINE OFFSET (F1)
WR_REG,TVP7000,0x01,0x46,0x1C // VBLK DURATION (F0)         
WR_REG,TVP7000,0x01,0x47,0x1C // VBLK DURATION (F1)         
WR_REG,TVP7000,0x01,0x48,0x00 // F-BIT START LINE OFFSET (F0)
WR_REG,TVP7000,0x01,0x49,0x00 // F-BIT START LINE OFFSET (F1)
WR_REG,TVP7000,0x01,0x4A,0xE3 // 1ST CSC COEFFICIENT LSB    
WR_REG,TVP7000,0x01,0x4B,0x16 // 1ST CSC COEFFICIENT MSB    
WR_REG,TVP7000,0x01,0x4C,0x4F // 2ND CSC COEFFICIENT LSB    
WR_REG,TVP7000,0x01,0x4D,0x02 // 2ND CSC COEFFICIENT MSB    
WR_REG,TVP7000,0x01,0x4E,0xCE // 3RD CSC COEFFICIENT LSB    
WR_REG,TVP7000,0x01,0x4F,0x06 // 3RD CSC COEFFICIENT MSB    
WR_REG,TVP7000,0x01,0x50,0xAB // 4TH CSC COEFFICIENT LSB    
WR_REG,TVP7000,0x01,0x51,0xF3 // 4TH CSC COEFFICIENT MSB    
WR_REG,TVP7000,0x01,0x52,0x00 // 5TH CSC COEFFICIENT LSB    
WR_REG,TVP7000,0x01,0x53,0x10 // 5TH CSC COEFFICIENT MSB    
WR_REG,TVP7000,0x01,0x54,0x55 // 6TH CSC COEFFICIENT LSB    
WR_REG,TVP7000,0x01,0x55,0xFC // 6TH CSC COEFFICIENT MSB    
WR_REG,TVP7000,0x01,0x56,0x78 // 7TH CSC COEFFICIENT LSB    
WR_REG,TVP7000,0x01,0x57,0xF1 // 7TH CSC COEFFICIENT MSB    
WR_REG,TVP7000,0x01,0x58,0x88 // 8TH CSC COEFFICIENT LSB    
WR_REG,TVP7000,0x01,0x59,0xFE // 8TH CSC COEFFICIENT MSB    
WR_REG,TVP7000,0x01,0x5A,0x00 // 9TH CSC COEFFICIENT LSB    
WR_REG,TVP7000,0x01,0x5B,0x10 // 9TH CSC COEFFICIENT MSB    

END_DATASET

  • 0
    TI__Genius 16810 points

    Hi Joe,

    The embedded syncs will be visible when you use the VESA mode.  This can be resolved by using a generics setup.  I will send you some setup data tomorrow.

    Regards,

    Larry

  • 0 in reply to Larry Taylor
    Prodigy 40 points

    Thanks Larry.  Looking forward for the gererics setup.

     

    Joe lam

  • 0 in reply to Joe Lam
    TI__Genius 16810 points

    Joe,

    Try the EVM setup below for generic 800x600x60Hz.   Attached are slides that show compare settings for some of the common graphics formats.

    Regards,

    Larry

    ////////////////////////////////////////////////////////////////////////////////

    BEGIN_DATASET  // Appended by WinVCC4 v4.50a.  Saved all registers.

    DATASET_NAME,"TVP7002+THS8200_SVGA60Hz-40MHz HS/VSin +/+ 4:2:2 embedded syncs YCbCr>RGB"

    //TVP7000
    WR_REG,TVP7000,0x01,0x01,0x42 // PLL DIVMSB      1056 pix/line            
    WR_REG,TVP7000,0x01,0x02,0x00 // PLL DIVLSB
    WR_REG,TVP7000,0x01,0x03,0x58 // PLL CONTROL                
    WR_REG,TVP7000,0x01,0x04,0x80 // PHASE SEL(5) CKDI CKDI DIV2
    WR_REG,TVP7000,0x01,0x05,0x06 // CLAMP START                
    WR_REG,TVP7000,0x01,0x06,0x10 // CLAMP WIDTH
    WR_REG,TVP7000,0x01,0x07,0x60 // HSYNC OUTPUT WIDTH - 96
    WR_REG,TVP7000,0x01,0x08,0x3C //Blue Fine Gain
    WR_REG,TVP7000,0x01,0x09,0x3C //Green Fine Gain
    WR_REG,TVP7000,0x01,0x0A,0x3C //Red Fine Gain
    WR_REG,TVP7000,0x01,0x0E,0x24 // SYNC CONTROL    HSout+ VSout+
    WR_REG,TVP7000,0x01,0x0F,0x2E // PLL and CLAMP CONTROL bit0 (0= HSPO by chip)
    WR_REG,TVP7000,0x01,0x10,0x58 // SOG Threshold-(RGB Clamp)
    WR_REG,TVP7000,0x01,0x11,0x40 // Sync Separator Threshold
    WR_REG,TVP7000,0x01,0x12,0x01 // PRE_COAST                  
    WR_REG,TVP7000,0x01,0x13,0x00 // POST_COAST
    WR_REG,TVP7000,0x01,0x15,0x43 // Output Formatter

    WR_REG,TVP7000,0x01,0x17,0x00 // MISC Control 2  FID out, Enable Outputs
    WR_REG,TVP7000,0x01,0x18,0x11 // Clock polarity  
    WR_REG,TVP7000,0x01,0x19,0xAA // INPUT MUX SELECT,    RGB CH3 selected      
    WR_REG,TVP7000,0x01,0x1A,0xCA // INPUT MUX SELECT, HSYNC_A and VSYNC_A selected, SOG and Clamp Filter
    WR_REG,TVP7000,0x01,0x21,0x0D // HSOUT START
    WR_REG,TVP7000,0x01,0x22,0x00 //               
                    
    WR_REG,TVP7000,0x01,0x26,0x80 // ALC RED and GREEN LSB      
    WR_REG,TVP7000,0x01,0x28,0x53 // AL FILTER Control          
    WR_REG,TVP7000,0x01,0x2A,0x87 // Enable FINE CLAMP CONTROL
    WR_REG,TVP7000,0x01,0x2B,0x00 // POWER CONTROL-SOG ON
    WR_REG,TVP7000,0x01,0x2C,0x50 // ADC Setup
    WR_REG,TVP7000,0x01,0x31,0x18 // ALC PLACEMENT
    WR_REG,TVP7000,0x01,0x35,0x00 // VSout Align
    WR_REG,TVP7000,0x01,0x36,0x00 // Sync Bypass
    WR_REG,TVP7000,0x01,0x3D,0x06 // Line Length Tolerance (Pixel Tolerance)

    WR_REG,TVP7000,0x01,0x40,0xEE // AVID Start 
    WR_REG,TVP7000,0x01,0x41,0x00 // AVID Start 
    WR_REG,TVP7000,0x01,0x42,0x16 // AVID  Stop
    WR_REG,TVP7000,0x01,0x43,0x04 // AVID Stop
    WR_REG,TVP7000,0x01,0x44,0x01 // VBLK F0 Offset (1)
    WR_REG,TVP7000,0x01,0x45,0x01 // VBLK F1 Offset
    WR_REG,TVP7000,0x01,0x46,0x1C // VBLK F0 Duration  28 lines
    WR_REG,TVP7000,0x01,0x47,0x1C // VBLK F1 Duration


    //THS8200//////////////////////////////////
    WR_REG,THS8200,0x01,0x03,0x01 // chip_ctl           
    WR_REG,THS8200,0x01,0x04,0x81 // csc_ric1           
    WR_REG,THS8200,0x01,0x05,0xD5 // csc_rfc1           
    WR_REG,THS8200,0x01,0x06,0x00 // csc_ric2           
    WR_REG,THS8200,0x01,0x07,0x00 // csc_rfc2           
    WR_REG,THS8200,0x01,0x08,0x06 // csc_ric3           
    WR_REG,THS8200,0x01,0x09,0x29 // csc_rfc3           
    WR_REG,THS8200,0x01,0x0A,0x04 // csc_gic1           
    WR_REG,THS8200,0x01,0x0B,0x00 // csc_gfc1           
    WR_REG,THS8200,0x01,0x0C,0x04 // csc_gic2           
    WR_REG,THS8200,0x01,0x0D,0x00 // csc_gfc2           
    WR_REG,THS8200,0x01,0x0E,0x04 // csc_gic3           
    WR_REG,THS8200,0x01,0x0F,0x00 // csc_gfc3           
    WR_REG,THS8200,0x01,0x10,0x80 // csc_bic1           
    WR_REG,THS8200,0x01,0x11,0xBB // csc_bfc1           
    WR_REG,THS8200,0x01,0x12,0x07 // csc_bic2           
    WR_REG,THS8200,0x01,0x13,0x42 // csc_bfc2           
    WR_REG,THS8200,0x01,0x14,0x00 // csc_bic3           
    WR_REG,THS8200,0x01,0x15,0x00 // csc_bfc3           
    WR_REG,THS8200,0x01,0x16,0x14 // csc_offset1        
    WR_REG,THS8200,0x01,0x17,0xAE // csc_offset12       
    WR_REG,THS8200,0x01,0x18,0x8B // csc_offset23       
    WR_REG,THS8200,0x01,0x19,0x15 // csc_offset3        
    WR_REG,THS8200,0x01,0x1C,0x53 // dman_cntl  20bit 422
    //sync tip and horizontal blank level setup        
    WR_REG,THS8200,0x01,0x1D,0x00 // dtg_y_sync1        
    WR_REG,THS8200,0x01,0x1E,0x00 // dtg_y_sync2        
    WR_REG,THS8200,0x01,0x1F,0x00 // dtg_y_sync3        
    WR_REG,THS8200,0x01,0x20,0x00 // dtg_cbcr_sync1     
    WR_REG,THS8200,0x01,0x21,0x00 // dtg_cbcr_sync2     
    WR_REG,THS8200,0x01,0x22,0x00 // dtg_cbcr_sync3     
    WR_REG,THS8200,0x01,0x23,0x2A // dtg_y_sync_upper   
    WR_REG,THS8200,0x01,0x24,0x00 // dtg_cbcr_sync_upper
    //horizontal timing setup
    WR_REG,THS8200,0x01,0x25,0x80 // dtg_spec_a         
    WR_REG,THS8200,0x01,0x26,0x00 // dtg_spec_b         
    WR_REG,THS8200,0x01,0x27,0x00 // dtg_spec_c         
    WR_REG,THS8200,0x01,0x28,0xD8 // dtg_spec_d         
    WR_REG,THS8200,0x01,0x29,0x00 // dtg_spec_d1        
    WR_REG,THS8200,0x01,0x2A,0x00 // dtg_spec_e         
    WR_REG,THS8200,0x01,0x2B,0x00 // dtg_spec_h_msb     
    WR_REG,THS8200,0x01,0x2C,0x00 // dtg_spec_h_lsb     
    WR_REG,THS8200,0x01,0x2D,0x00 // dtg_spec_i_msb     
    WR_REG,THS8200,0x01,0x2E,0x00 // dtg_spec_i_lsb     
    WR_REG,THS8200,0x01,0x2F,0x28 // dtg_spec_k_lsb     
    WR_REG,THS8200,0x01,0x30,0x00 // dtg_spec_k_msb     
    WR_REG,THS8200,0x01,0x31,0x00 // dtg_spec_k1        
    WR_REG,THS8200,0x01,0x32,0x00 // dtg_speg_g_lsb     
    WR_REG,THS8200,0x01,0x33,0x00 // dtg_speg_g_msb     
    WR_REG,THS8200,0x01,0x34,0x04 // dtg_total_pixel_msb
    WR_REG,THS8200,0x01,0x35,0x20 // dtg_total_pixel_lsb
    WR_REG,THS8200,0x01,0x36,0x00 // dtg_linecnt_msb    
    WR_REG,THS8200,0x01,0x37,0x01 // dtg_linecnt_lsb    
    WR_REG,THS8200,0x01,0x38,0x89 // dtg_mode  Generic SDTV        
    WR_REG,THS8200,0x01,0x39,0x22 // dtg_frame_field_msb
    WR_REG,THS8200,0x01,0x3A,0x74 // dtg_frame_size_lsb 
    WR_REG,THS8200,0x01,0x3B,0x74 // dtg_field_size_lsb 
    WR_REG,THS8200,0x01,0x3C,0x80 // dtg_vesa_cbar_size 
    //CSM setup to map YCbCr to FS RGB        
    WR_REG,THS8200,0x01,0x41,0x40 // csm_clip_gy_low    
    WR_REG,THS8200,0x01,0x42,0x40 // csm_clip_bcb_low   
    WR_REG,THS8200,0x01,0x43,0x40 // csm_clip_rcr_low   
    WR_REG,THS8200,0x01,0x44,0x53 // csm_clip_gy_high   
    WR_REG,THS8200,0x01,0x45,0x3F // csm_clip_bcb_high  
    WR_REG,THS8200,0x01,0x46,0x3F // csm_clip_rcr_high  
    WR_REG,THS8200,0x01,0x47,0x40 // csm_shift_gy       
    WR_REG,THS8200,0x01,0x48,0x40 // csm_shift_bcb      
    WR_REG,THS8200,0x01,0x49,0x40 // csm_shift_rcr      
    WR_REG,THS8200,0x01,0x4A,0xFC // csm_mult_gy_msb    
    WR_REG,THS8200,0x01,0x4B,0x44 // csm_mult_bcb_rcr_msb
    WR_REG,THS8200,0x01,0x4C,0xAC // csm_mult_gy_lsb    
    WR_REG,THS8200,0x01,0x4D,0x91 // csm_mult_bcb_lsb   
    WR_REG,THS8200,0x01,0x4E,0x91 // csm_mult_rcr_lsb   
    WR_REG,THS8200,0x01,0x4F,0xFF // csm_mode           
     
    //Generic Mode Line Type Setup. Set dtg_bp 2_msb and lsb to 629 (lines per frame +1) 
    WR_REG,THS8200,0x01,0x50,0x02 // dtg_bp1_2_msb     /////////////// /
    WR_REG,THS8200,0x01,0x58,0x00 // dtg_bp1_lsb        
    WR_REG,THS8200,0x01,0x59,0x75 // dtg_bp2_lsb          /////////////////////  
           
    WR_REG,THS8200,0x01,0x68,0x00 // dtg_linetype1  = active video
    WR_REG,THS8200,0x01,0x69,0x00 // dtg_linetype2   = active vieo   


    WR_REG,THS8200,0x01,0x70,0x80 // dtg_hlength_lsb    
    WR_REG,THS8200,0x01,0x71,0x00 // dtg_hdly_msb       
    WR_REG,THS8200,0x01,0x72,0x01 // dtg_hdly_lsb       
    WR_REG,THS8200,0x01,0x73,0x05 // dtg_vlength_lsb    
    WR_REG,THS8200,0x01,0x74,0x00 // dtg_vdly_msb       
    WR_REG,THS8200,0x01,0x75,0x01 // dtg_vdly_lsb       
    WR_REG,THS8200,0x01,0x76,0x00 // dtg_vlength2_lsb   
    WR_REG,THS8200,0x01,0x77,0x07 // dtg_vdly2_msb      
    WR_REG,THS8200,0x01,0x78,0xFF // dtg_vdly2_lsb      
    WR_REG,THS8200,0x01,0x79,0x00 // dtg_hs_in_dly_msb  
    WR_REG,THS8200,0x01,0x7A,0x51 // dtg_hs_in_dly_lsb  
    WR_REG,THS8200,0x01,0x7B,0x00 // dtg_vs_in_dly_msb  
    WR_REG,THS8200,0x01,0x7C,0x01 // dtg_vs_in_dly_lsb  
    WR_REG,THS8200,0x01,0x82,0x3B // embedded syncs and pol_cntl           


    END_DATASET

    THS8200 YCbCr to Graphics RGB 072810.ppt