Hello,
I am using a Xilinx Kintex Ultrascale evaluation card (KCU105) connected to a DAC38J84EVM to test out some designs. I am able to successfully initiate a JESD204B link between the FPGA and DAC when I configure the FPGA core and DAC to run in LMF = 442 mode and can generate waves as expected.
My issue is that if I reconfigure the devices for LMF = 421 mode with HD = 1, I cannot get the link to establish. At the end of the ILA sequence the SYNC signal deasserts for a few clocks and then reasserts. This pattern happens continuously. I've captured the ILA sequence that the FPGA transmits to the DAC, and all the values match the appropriate DAC configuration registers. If I then modify register config79 (0x4F) by setting bit 5 to 1 (to ignore lane configuration errors), the link is established and I can generate waves as expected. Have you ever seen this before?
The other common parameters for both configurations are as follows:
S = 1
K = 16
RBD = 15
Lane Rate - 4.8Gbps
Interpolation - 4x
FPGA clock - 120 MHz
DAC clock - 960 MHz
Thanks,
Andy
