Hi.
I'm developing an Analog to Digital frontend,
In my project I've used two ads5542, they are drive by a Xilinx FPGA. Thanks to the FPGA i'm able to drive the ADC by an asyncronous reset, to able/disable the input clock or to configure registers by the serial interface.
First of all I tried to give to the ADC an asyncronous reset, widley longer than request. The ADC is supposed to start to run after the falling edge of reset signal.
No clock out at all or data output switch or OE assertion, just an increase of power dissipation, it suggests that the ADC is not in POWER DOWN anymore.
I proved that by disabling input clock, the ADC goes to the POWER DOWN state as described in the datasheet and after i gave to it that a reset input that will forced it to get out from this state. It works, power dissipation increased as well as I expected, but no switching from outputs.
Then I tried to program the ADC by serial interface, I've discovered that the ADC go right in POWER DOWN mode also in this case and get out of it by the two right words. All the other configurations for testing procedure don't work at all. And I still have no Outputs.
I checked all the layout to verify it there was a bug on it but it's fine.
Can somebody suggest to me how to solve this problem?i
Alex R.
