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ADS8865: In daisy chain mode, must CONVST fall low on the low of the SPI clock?

Tom Oldbury
Intellectual 540 points
Part Number: ADS8865
Other Parts Discussed in Thread: TM4C123GH6PM

I am using an ADS8865 in daisy chain configuration with one other device.

The devices are configured as shown on page 26 of the datasheet.

I notice in the timing diagram that CONVST falls low exactly on the SPI clock falling low. Currently, my CONVST falls low after the SPI peripheral on my TM4C123GH6PM signals an end-of-transmission interrupt' this happens about 1us after the last SPI clock falling edge.

The data I'm getting seems to be corrupt - out of sync by one sample. Could this be the issue?

Kind regards

  • 0
    TI__Guru 55466 points

    Hello Tom, 

    I will need to  verify if there is a strict requirement of having CONVST falling low exactly as the last SCLK falling low.  Please allow three business days and I will confirm with the design group and/or bench.

    If you could please provide an oscilloscope plots of the CONVST, SCLK, DOUT1, and  DOUT2 we could also verify your timing.

    Thank you and Best Regards,

    Luis

  • 0 in reply to Luis Chioye
    TI__Guru 55466 points

    Hello Tom,

    Looking through Timing Requirements: Daisy Chain (Table 3, p7 on the ADS8865 datasheet), there is no strict  timing parameter specification involving the CONVST falling edge with respect to SCLK; therefore CONVST is not required to be synchronous to SCLK.  The requirement is that CONVST must remain high from the start of conversion until all data bits are read. 

    However, when using the device in Daisy-chain Mode Without a Busy Indicator (DIN=0), the datasheet recommends that SCLK must be low at the CONVST rising edge so that the device does not generate a busy indicator at the end of conversion; and defines the following timing parameters regarding SCLK and CONVST on Figure 3,  p7:

    tsu-CK-CNV Setup time: SCLK valid to CONVST rising edge (5ns min)

    th-CK-CNV Hold time: SCLK valid from CONVST rising edge (5ns min)

    If possible, please provide a couple of oscilloscope plots with CONVST, SCLK,  DOUT2 so we can verify the timing.

    Thanks and Regards,

    Luis

  • 0 in reply to Luis Chioye
    Intellectual 540 points

    Thanks Luis,

    I resolved the issue. It was due to an SPI data offset. I was writing some additional bytes beforehand, so every two bytes I read out were for the previous channel.

    I can confirm that my ADS8865 appears to not have any issue with the falling edge of CONVST being delayed from the last falling edge of SCLK.

    Kind regards

  • 0 in reply to Tom Oldbury
    TI__Guru 55466 points
    Hi Tom,

    Glad to hear the issue was resolved, and thank you for the confirmation regarding CONVST falling edge.

    Kind Regards,
    Luis