Other Parts Discussed in Thread: AFE7071
hello.
i have a question about the AFE7071's internal DACs
in single ddr clock mode the I DAC latches a new value on the rising edge and the Q DAC latches a new value on the falling edge.
my question is : are the 2 DAC outputs updated at the same time or is each output updated immediatly when it latches a value?
(logically the two outputs should update at the same time, but the datasheet does not give an answer)
