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Vertical & Horizontal Sync Loss - TVP5147PFP

Other Parts Discussed in Thread: TVP5147, TVP5147M1

Hello,

 

I have a custom board with a TVP5147PFP. I am using this to decode a B/W PAL signal. The input PAL signal seems to drive a monitor just fine. But when the same input signal is given to the TVP5147, i get a vertical and horizontal sync signal loss from status register 0X3A and there is no output from the CLOCK, HS, FS pins. These are the settings of the TVP5147 :

 

a) Input given to VI_1_A (Pin 1) - Inputs are terminated with 75ohm and ac coupled through a 0.1uF capacitor.

b) All registers are at their power on defaults( i guess this means that autoswitch is enabled)

c) I2C reads from the device seems to be working fine and i am able to read CHIP ID registers successfully.

d) My clock is a fundamental 14.31818 MHz crystal with load capacitors calculated as per the datsheet recommendations.

e) Power Supplies (1.8V, 3.3V) have sufficient decoupling and am using ferrite beads for low passing the supply to remove residual ripple, if any

f) PWDN pin is pulled low and reset is proper.

g) I am using separate analog and digital grounds on my circuit board and am tying them together by means of a ferrite bead.

Could someone kindly explain if this is caused by a hardware issue or am i not configuring the TVP5147 properly ? I have verified the line and frame timings of my input signal and it seems to be fine.

Any help would be greatly appreciated. I can post scope shots of my signals and register dumps if needed...

Thanks!

Sornam

 

 

  • Hi Sornam,

    Could you please try toggling the power save bit in REG 03h to see if it resolves this issue?

    Do you have pull-down resistors installed on Pins 69 and 71?  This could affect the power-up state of the TVP5147M1 and is recommended.

    Regards,

    Larry

     

  • Sornam,

    Were you able to resolve your lock issue?

    Regards,

    Larry

  • Hello Larry,

    Sorry for the late response. Here are a few updates to my earlier post.

    a) On careful examination of the datasheet, i came to understand that the outputs (CLK, Data, HS, VS, AVID, FID) are either tristated or inputs on power on reset. Hence, i configured the control registers for these pins to output data.

    b) I have also configured the TVP5147 to output data  ; 20 bit 4:2:2 @ pixel rate with separate syncs. I am able to get a stable HS @15.625 Khz and a stable VSync @49.99 Hz .

    c) I am reading the registers immediately after power on. They however seem to be indicating lock lost, eventhough i am able to get these sync signals out corectly.

    Right now, i am looking at passing through the data that i am able to obtain to a video dac and display it on the monitor. Will keep you posted on the goings on .

    Regards,

    Sornam

     

     

     

     

     

  • Hello Larry,

    Here is another update.

    I guess i made a mistake when i said that i was getting a stable Hsync and Vsync out with the registers indicating lost lock. I read the registers immediately after power up and did not read the registers again. But the registers do indicate that horizontal and vertical syncs are indeed getting locked , if i read the registers after a delay.

    I have been able to pass an image through the video decoder - > to a video dac -> and drive a monitor successfully.

    I am however looking to tweak the register settings to optimise the image obtained further.

    Thanks!

    Sornam

     

     

     

  • I have a similar issue: VPIF captures frames normally except image split(vertical lock loss), but TVP5147m1 register 0x3a always returns 0x71 whether video input connected or not.

    Any suggestions are appreciated.

  • I have a similar issue: VPIF captures frames normally except image split(vertical lock loss), but TVP5147m1 register 0x3a always returns 0x71 whether video input connected or not.

    Any suggestions are appreciated.