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DAC39J84: configuration about DAC39J84

An liu
Prodigy 100 points
Part Number: DAC39J84


 I'm working on a project which using the dac39j84 and lmk04828b. After reading the datasheets of them, I have some questions as follows：

1. Can I assign all the eight lanes to one link? Or  four lanes must to be assigned to link0 and the rest four lanes to link1?

2. What is the meaning of did (device id) and bid(bank id)? I don't understand what the bank refers to? If I want to use all lanes for one link,do I need to config registers related to did and bid?

3.how can I meet the requirement the setup and hold time between device clock and sysref clock? And I didn't find the specific requirement between this two clocks in the datasheet of dac39J84 

looking forward to your replies

Thank you  

  • 0
    TI__Guru* 91947 points

    An,

    Let me know if you got the answer to these in a previous post.

    Regards,

    Jim

  • 0 in reply to jim s
    Prodigy 100 points
    Jim,
    Yes, I have got the answer from your previous private message. And I did solve some of the problems with your help. Thank you for your support. And now I'm trying the 12Gb/s lane rate. The DAC39J84 can run normally for a few minutes and then the synchronization is lost. And sometimes the SYNC signal is low and then re-high in a short time. Is there anything to be taken care of when we config the registers or generate the clock?
    Regards,
    An
  • 0 in reply to An liu
    TI__Guru* 91947 points

    An,

    Can you clear then read the DAC alarms to find out what may be the problem? Did you try running the PRBS test?

    Regards,

    Jim

  • 0 in reply to jim s
    Prodigy 100 points
    Jim,

    Thank you for your reply. Yes, I clear the alarm registers and then read them. And the error is multi-frame alignment error and frame alignment error. I try to reduce the RBD value and K, but it dosen't work..I can see the anolog wave came out for just a few moment and then DAC39J84 lost its synchronization.
    I didn't try running the PRBS test and I'll try it tomorrow.

    Regards,

    An
  • 0 in reply to An liu
    TI__Guru* 91947 points

    An,

    it appears SYSREF is not at the correct frequency. Double check that you are using the correct value for K at both ends and that the value of K meets the following JESD204B standard:   17< F * K < 1024.

    Regards,

    Jim

  • 0 in reply to jim s
    Prodigy 100 points

    Jim,

    Thank you for your reply. I check my SYSREF frequency and the K value and they are correct. Can you help me run the 12Gb/s on the EVM board with my configuration?

    DAC: device clock is 300MHz

              sysref clock is 18.75MHz

    FPGA: device clock is 300MHz

                sysref clock is 18.75MHz

                refclk clock is 300MHz

    The configuration of DAC39J84 is in the excel. Thank you.

    Regards,

    An

    DAC configuration_12Gbps.xlsx

            

  • 0 in reply to An liu
    TI__Guru* 91947 points

    An,

    I am on vacation until April 18th. If you need immediate assistance, please open a new E2E post and someone should reply soon.

    Regards,

    Jim

  • 0 in reply to jim s
    Prodigy 100 points
    Jim,

    Thank you for your reply. I'll try to ask somebody else for help and check my configuration again.

    Have a nice vacation! ^_^

    Regards,

    An