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ADC12J4000EVM: Spurious levels in ADC12J4000EVM

Part Number: ADC12J4000EVM


Hello,

I am seeing high spurious levels in ADC data when connected to a signal generator. The SERDES does not show any error as is locked all the times. The spurious levels are around 25-30 dbc. Can somebody help me how to improve the levels.

Thanks,

D

  • Hi D

    With spurs at that level I expect you are seeing high levels of harmonics coming from the signal generator.

    Ensure you have a good quality signal generator and use a bandpass or lowpass filter to remove harmonics from the signal applied to the ADC inputs.

    If possible save a screenshot of the results you are getting and attach them to your next post.  Click on the Use rich formatting link at the bottom right of the response box and you'll see more options including ones to attach images or files.

    Best regards,

    Jim B

  • Hello Jim,

    I agree  higher level of harmonics and noise floor  can be coming from other  sources. I will update you more when I nail down issue a little more. However,  I saw many options with calibration as in configuration GUI. Are these mandatory to be turned on, or shall be done as needed ? Is there something else that can be worked on to minimize these issues ?

    Thanks,
    D

  • Hi D

    The ADC12J4000EVM GUI configures the ADC into foreground calibration mode with timing calibration enabled. Calibration will be performed at the end of the initial configuration writes when the Program ADC and Clocks button is clicked.

    Here is an example FFT with a 497 MHz input signal showing the expected performance with a clean source:

    To re-optimize performance navigate to the Control tab and click on the "Execute Foreground CAL" button. This toggles the CAL_SFT bit to trigger the foreground and timing calibration processes.

    Best regards,

    Jim B