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Sampling high frequence narrow-bank signals with low sampling rate

Yefu
Intellectual 365 points

This is a general question, no special device

 For example:

The signal's center frequence  is 100M,  whose bank is 20M.

It means that the signal frequence is 90M~110M

But the sampling rate is 50MSPS

How can we reconstruct this high frequence signal with low sampling rate?

Thank you very much

 

Yefu

 

  • 0
    Expert 1710 points

    The 50MS/s signal will carry all the modulation information possible in a 20 MHz bandwidth signal, as long as the input signal is truly band limited to 20 MHz.

    In practice, though it may be easier to either downconvert the signal to an intermediate frequency such as 2-22 MHz prior to sampling with the ADC or to use

    some kind of I/Q quadrature based down conversion sampling scheme to help convert the signal to a sampled baseband 0-20 MHz spectrum signal.

    http://en.wikipedia.org/wiki/Low_IF_receiver

    http://www.eetimes.com/design/automotive-design/4007644/DSP-Tricks-Interpolating-a-bandpass-signal

    http://www.am1.us/Papers/U11618%20Receiver%20Architectures.pdf

    http://www.hunt-dsp.com/pdfs/tech/ddctheory.pdf

     

     

     

  • 0 in reply to C. Hayes
    TI__Intellectual 1965 points

    However, we warned, if the clock frequency is 50MHz and the signal bandwidth of interest is 90-110MHz, you will get the 90-100 and the 100-110 aliased ontop of each other.  Normally it is recommended to place all the of 20Mhz into only one Nyquist band.  With a clock freq of 50MHz, the Nyquist bands are

    Nyquist band 1: 0-25MHz

    band 2: 25-50MHz

    band 3: 50-75MHz

    band4: 75-100MHz

    band5: 100-125MHz

    Also, you need to bandpass filter the IF band in order to only allow energy into the ADC analog inputs from the Nyquist band you want, otherwise the ADC will alias all the bands into 1st nyquist (in the digital output), up to and beyond the 3dB bandwidth of the ADC inputs.  The AAF (anti-alias filter) will need some transition band, so with a 50M clock and 20MHz BW of interest, you might not really have enough overhead.  If the IF is fixed at 90-110MHz and cannot be changed, I'd recommend a clock frequency more like 80MHz.  This puts 90-110MHz dead center into the 3rd Nyquist band of an 80MSPS clock.  It will alias down and come out in the digital FFT as 10-30MHz.  Gives you 80-90MHz and 110-120MHz for AAF transition band.

  • 0 in reply to Philip Pratt
    Intellectual 365 points

    Thank you for your reply

    Your reply presents lots of information, so I need time to understanding.

    On your suggestion, let's set the clock clock frequence at 80MHz, and I also place a 90M-110M band pass filter in front of ADC.

    But I don't know how to reconstruct this signal?

     Yefu

  • 0 in reply to Yefu
    TI__Intellectual 1965 points

    The ADC will automatically think its sampling from 10-30MHz (it is tricked) , so this is where it will show up in the digital pattern that is running out at 80MSPS (if you grabbed 2^n samples and ran a DFT).

    If you ever try this test with a real ADC, you need to make sure the analog input test frequency (tone) is coherent with the number of samples you choose to grab and process.  You want all of the tone in 1 exact bin of the DFT, otherwise it looks funny and you would need to use windowing to fix it (but that's ok too).

    Take the clock freq and divide by number of FFT samples you want.  This gives you the freq step sizes available to stay coherent.  Like 80MHz / 16384 = 4882.8125 Hz.  Make sure the frequency you inject is an exact multiple of this bin size, or use a windowing function if you cannot be coherent.  If the ADC is >10-12bits, you will probably need to use very clean clock and analog generators, and will probably need to bandpass filter both the clock and analog sources to get everything clean for the test and match the datasheet, and measure the ADC not the equipment.