• State
  • Locked Locked
  • Replies 1 reply
  • Subscribers 46 subscribers
  • Views 888 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADC128S102: Power Down VA vs SPI Bus

James Becker18
Prodigy 120 points
Part Number: ADC128S102


In our application we have two separate +3.3V regulators.  One supplies power to the VA/VD pins, and one powers the FPGA that outputs the SPI bus to the ADC. Though both regulators are powered by the same +5V source, they may power-down at a different rate that causes the SPI bus voltages to be greater than the VA/VD voltage.  Is this a problem?  In the data sheet on page 17, paragraph 7.3.3 Digital Inputs and Outputs, it states:   "The digital inputs of the ADC128S102 (SCLK, CS, and DIN) have an operating range of 0 V to VA.  The inputs are not prone to latch-up and may be asserted before the digital supply (VD) without any risk."

Do you see any issue with the SCLK, CS, & DIN if they exceed VA/VD for ~200ms at power-down?

Thanks,

Jim Becker
Raytheon SAS
El Seguno, CA

  • 0
    TI__Expert 5575 points

    Hi Jim

    As per data sheet digital inputs can be asserted before digital supply is up (but need to make sure they do not violates recommended operating condition)

    One thing we can do is to replicate your use case on one of the ADC128S102 device and see if we can give you some real time data.

    Thanks and Regards

    Abhijeet