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DAC39J84: SYSREF to Device Clock Alignment

An liu
Prodigy 100 points
Part Number: DAC39J84


The datasheet of DAC39J84 points out that the setup time and hoId time is 50ps. And in my design I chose LMK04828b as clock source and used fixed digital delay mode to adjust the relationship between sysref

clock and device clock.  

The total delay time of SYSREF clock is (X+Y)/(frequency of VCO), where  X is the value of register13C and 13D, Y is the value of register104/10C/114/11C/124/12C/134.

The total delay time of Device clock is Z/ (frequency of VCO), where Z is the value of register101/109/111/119/121/129/131.

In my design, frequency of VCO is 2400MHz, sysref is 9.375MHz, and device clock of FPGA is 150MHz, device clock of DAC39J84 is 600MHz.

And no matter what value I config the value of X, Y, Z, I can't meet the requirement of 50ps. And the delay time of SYSREF clock is always longer than the Device clock for the X is at least 8. 

Can you help me? How to meet the relationship  requirement between sysref clock and device clock .

  • 0
    TI__Guru* 91947 points

    An,

    What VCO is at 2400MHz, the LMK? What is the reference clock frequency used by the LMK? Did you route the device clock and SYSREDF traces the same length to your DAC? This is critical that you did this. How are you measuring setup and hold times? There should not be any issues at these frequencies. What is your "K" value? What is your DAC output data rate? What LMF settings are you using? I will try to duplicate your setup.

    Regards,

    Jim

  • 0 in reply to jim s
    Prodigy 100 points
    Jim,

    yes, I use the LMK04828b and the frequency of VCO0 in PLL2 is 2400MHz. I choose the dual pll mode and make clkin0 to be my input clock source.
    An external 600MHz clock offered by Agilent's signal source is the reference clock. Yes, I route them the same trace ,the length of device clock to
    DAC is 1953.26mil, the length of sysref clk to DAC is 1911.22mil. Will this little difference effect the timing?
    My configuration is L=8, K=32=RBD, M=4, F=1, HD=1,DAC's output data rate is 600MSPS , line rate is 6Gbps
    FPGA: device clock is 150MHz,length is 4187.01mil ; sysref clock is 9.375MHz , length is 4185.37mil
    DAC: device clock is 600MHz, length is 1953.26mil; sysref clock is 9.375MHz, length is 1911.22mil

    I just calculate the frequency relationships and don't know how to measuring setup and hold times. Can you tell me? And are the formula I gave out in the last post right? I really don't know how to set the value of X Y Z to meet the 50ps required by DAc39J84.

    Thank you for your kindness

    Best regards

    An