This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADC10065: Question about oscillation the VREF and Vcom

Guru 19645 points
Part Number: ADC10065

Customer problem for ADC10065 VCOM, VREFT, and VREFB, waveform is attached below.

ADC10065_Vcom_unstable.pptx

Please let me know about three points below.

①Are these oscillation normal operation? 

 Is this oscillation happen normally?

②Please let me know about the theory of oscillation. 

③On the datasheet, specification for Internal reference is no described.

 Is there spec information for internal reference?

【Additional information】

I think that the one of cause is customer's passive probe.

But previously, I want to know ADC10065's trend of operation. 

Best regards,

Satoshi

  • Hi Satoshi

    1, 2) I'm reviewing the product information to understand why the Vcom voltage may be shifting like that in their usage.

    Can you get the customer to try using a continuous instead of burst mode clock to see how the Vcom voltage behaves in that condition?

    3) All datasheet specifications assume a continuous clock. The internal Vref is listed as 1.2V typical and the Vcom is listed at 1.45V typical. You are correct, there are no limit specifications for these parameters in the datasheet, only a Vreftc spec for variation versus temperature.

    Thanks,

    Jim B

  • Jim-san

    Thank you for reply,
    I looking forward your update.

    Best regards,
    Satoshi
  • Hi Satoshi

    I haven't found any documentation that explain the shifts shown in the customer results.

    Has the customer followed my recommendation to try testing with a continuous clock to see how the Vcom and VREF behavior changes?

    Jim B

  • Jim-san

    Thank you for check.

    Please see customer update below;

    ⇒For tensing with a continuous clock, VCOM was stable.

     ・TXADC_CLK:stop

    ・TXADC_CLK:continue

    Is ADC10065 have bad influence for the condition of TXADC_CLK:ON and OFF?

    Best regards,

    Satoshi

  • Hi Satoshi

    The ADC10065 was not designed or evaluated for rapid start/stop of the CLK during signal acquisition.

    The intention is that the ADC clock is stable and continuous.

    Best regards,

    Jim B

  • Jim-san
    Thank you for reply,

    Please let me know about relation of VCOM and Clock for ADC10065 internal circuit.
    ①About rapid start/stop, I think that device is forced shutdown when after clock stopped, is it correct?
    ②If correct, I guess that device shutdown and abnormal current is flow internal circuit.
    Is there internal circuit information for current flow (Current capacity, route, etc)?
     ※If any information, I maybe understand relation of VCOM and Clock.

    Best regards,
    Satoshi
  • Hi Satoshi

    The original designers of the ADC10065 are no longer at TI so I haven't been able to get more detail on the internal relationship between VCOM and clock.

    I can't explain why the voltage on VCOM shifts when the clock is stopped, and don't have any recommendations on ways to change this behavior.

    Best regards,

    Jim B