Part Number: ADS4449
Hello,
we want to use the ADC ADS4449 with a Xilinx FPGA in a complex clock network. The capturing of the data is not a problem. The problem is the complex system timing of more than one ADC ADS4449 and FPGA. In the datasheet page 10, chapter 6.7, “Timing Requirements” – “Output Timing” shows the specification of the “Delay time”. The max and min Delay time is given for the full temperature range from -40°C to +85°C. But these values are too critical for our system timing.
The questions are:
1. How are the max and min values for the Delay time specification in a reduced temperature range of 0°C to 70°C?
2. Includes the Delay time specification the min and max values of the variable Delayed output clocks by the register settings?
