ADC32RF45EVM: cfg files for internal clk 14-bit operation

Hi,

Do you have the latest SPI GUI from the TI web?  The config files included with the latest GUI are named as follows for the internal clocking LMX2582 option 14bit bypass:

LMK_ADC32RF45_bypass_2949Msps.cfg

LMX_2949p12M.cfg

ADC32RF45_8224.cfg

NL_Config_Nyq1.cfg  (or Nyq2 or Nyq3)

Also, there is a quick-setup tab to make the selection easy.  Choose the clocking option, and for internal clocking choose the clock rate, then choose the mode of operation for the ADC, and then press PROGRAM EVM.   All the PROGRAM EVM button does is load the proper config files for the mode of operation chosen.

We have chosen to set up all of the config files for a K value of 16, along with the HSDCPro ini files to match.  That means there may be different SYSREF divider values programmed into the LMK for the different ADC modes of operation, as well as different divider values for the reference clock from the LMK04828 back to the FPGA on the capture card.  To keep the LMK and LMX programming files the same for 12bit or 14bit bypass modes, or the same for all the different DDC modes, we set these couple of LMK values in the ADC config file.   Open the config files with an editor and you may see the last thing written is the LMK clock divider for the clock to the FPGA, for example.   This helps us keep the rest of the LMK config files the same across a number of modes of operation and not have to have an LMK file for each and every ADC file.

The input impedance of the analog input is nominally 50 ohms, but it may not be quite flat at 50 over the range of frequency.  Also, the input baluns on the channels can have some part to part variation in their loss properties.

Regards,

Richard P.

Downloaded the GUI and used the PROGRAM EVM it seems to work. Thank you.

The following error message would come out running HSDC in continuous mode, after 10 to 30 minutes and after restart capture.

Is this a hardware issue or GUI? Is the source code (VI's) for the HSDC Pro available in Shared, or can you point to the basic building VI's to build a simple loop, if HSDC Pro is proprietary software?

Also the chip runs quite hot, would this be an issue or do you recommend cooling?

Hi,

when you choose the 'device' mode of operation (ADC32RF45_LMF_8224) and set the data rate to 2.949Msps, what does the popup window say the lane rate for the JESD204B is?    Did you choose that same clock rate when you used the SPI GUI?   The max sample rate for 14bit mode LMFS_8224 is 2.5Gsps.    At that max sample rate of 2.5Gsps the line rate of the JESD204b link is 12.5Gbps, which is the max rate for both the ADC and for the TSW14J56.    If you are really running the EVM at 2.949Gsps in 14bit bypass mode then the lane rate would be approaching 15Gbps.   That is way outside spec.  I wouldn't expect it to operate at all, so I am wondering if the EVM SPI GUI were really set to a different clock rate.

The EVM does get hot, but that is why we have the heatsink under the ADC, to keep it from getting too hot.   We will sometimes also have a small USB-powered bench top fan on the bench about a foot away to move some air past the EVM as well.

I will let someone else address the source code for the HSDCPro.  But it is proprietary software.

Regards,

Richard P.

The pop up window below is for 2.949G and 2.5G setup, respectively. Running 2.5G setup for an hour by now the same error message came back again. Same thing for 2.0G. It might've taken longer than 2.949G, however.

Is the JESD ref clk set automatically on clicking OK, or you have to set them somewhere?

Hi,

The divider integer in the LMK04828 for the FPGA clock is set by the config files that come with the SPI GUI, which for the LMFS_8224 mode is:

LMK04828
0x10F 0x06   //Disable SYSREF from LMK to ADC
0x10E 0xF1   //Disable SYSREF from LMK to ADC
0x100 0x08  // clock divider to 8

So in the config file for the LMFS_8224 mode you can see that the last thing the config file does is set the FPGA clock divider to 8, which for 2.5GHz would provide a clock of 312.5MHz to the FPGA.    When you use the Quick Setup tab in the SPI GUI and the PROGRAM EVM button, all that button does is load the appropriate config files.   So for all the modes of operation supported by the Quick Setup tab the config files chosen should have bee previously checked out to set that divider properly.

If the continuous capture feature of the HSDCPro is not running forever but errors out after a period of time, that may be something we would have to have the software team look into. 

Regards,

Richard P.

Just an update I was able to run at 2.5G setting or no change to your recommended setting without any error for the past 14 hours where I had pointed a hair dryer to the chip. This confirmed that all cfg files are correct but I will need additional cooling in the final design. It can close now.

Pls do get back to me about how to build a customized GUI with some of the HSDC VI's. Thank you for your help.

Hi,

the HSDCPro GUI was architected with the actual User Interface written in Labview, but there were C-code DLLs created to handle the hardware transactions to the capture card.  That is why the HSDCPro can disconnect from one type of capture card such as TSW1400 and then connect to a completely different one like TSW14J56.  There are different C-code DLLs one for each type of hardware but a common interface to the Labview.   These DLLs are not documented for public support however.  In theory you could create your own replacement for HSDCPro by communicating with the DLLs, but support for those proved to be unmanageable.  Instead the HSDCPro offers the support for automation by letting some higher level program control HSDCPro, but that is by having the automation program control HSDCpro and the data from the EVM flows through the DLL and the HSDCPro to the automation program - it does not eliminate HSDCpro.

So that is what is supported at present - the option to have programmatic control of HSDCPro.   The alternative on your end would be to create your own FPGA firmware and the GUI to support it.

Regards,

Richard P.