ADS1232: Common and normal mode rejection at 80sps

Hi Scott,

Welcome to the forum!  The ADS1232 uses a sinc4 digital filter and filter notches will appear at the data rate and multiples of the data rate.  Figure 31 on page 16 of the ADS1232 datasheet shows the behavior.  As 50 and 60 Hz are multiples of 10 Hz, then at 10sps you will see notches at 50 and 60 Hz.

The same filter behavior occurs at 80sps, but the notches are now at 80Hz and multiples of 80 (160, 240, 320 Hz etc).  So 50/60 Hz are within the pass band of the digital filter.  The response is the same as Figure 31(a) accept the x-axis would now show the notches at the appropriate values of 80, 160, 240, 320 Hz, etc..   For 80sps there is little to no rejection of 50/60 Hz.

Best regards,

Bob B

Thanks for that information. Is there any technique that could provide 50/60Hz rejection at the higher sampling speed with this chip?

Hi Scott,

You could apply external filtering.  The problem with external filters is analog settling delay for any change in sensor output with cutoff frequencies low enough where 50/60 Hz filtering is effective.

As noise also increases with data rate, is there a specific reason you need to operate at 80sps?  Is this a load cell application or some other type of measurement?

Best regards,

Bob B

Hi Bob,

Thanks for getting back to me. This is a load cell application, and I am trying to get a fix as fast as I can. Since a load cell typically has a rather long settling time, I am hoping to obtain a faster fix by taking samples during that time and using those values to calculate the final resting value.

How is this ADC used at the higher sampling rate without the 50/60Hz rejection? This is a new design area for me - I am assuming the noise contribution from A/C hum is significant. How significant is it, and how can I mitigate it at the higher sampling rate? Is physical shielding sufficient? I assume the measurement cable would need to be shielded also?

Thanks,
Scott

Hi Scott,

Initially you asked about common-mode and normal-mode rejection at 80sps.  I should have stated that the common-mode rejection will be the same for both 10sps and 80sps.  It is the normal-mode that differs due to the sinc filter notch.

Line-cycle noise can be significant and should be eliminated if at all possible prior to the ADC.  The biggest source of the problem occurs on the load cell cabling, so you should use a shielded cable that is properly terminated.  Keep in mind too that at 80sps the noise is much more significant and your resolution will drop due to the conversion noise, so the line-cycle noise may be within the level of the conversion noise.

One other approach is to run at 10sps when the weight is stable, but if the weight changes (by a specific number of codes) adjust the speed to 80sps, and when the code fluctuations start to stabilize switch back to 10sps.  This helps with scale settling with respect to the digital filter (sinc4), but allows the line-cycle rejection at the measurement.  For this to work you need to create an algorithm specifically to accomplish this task.

Best regards,

Bob B