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ADS54RF63: Signal reflections in combination with a Xilinx FPGA

user4946482
Prodigy 40 points
Part Number: ADS54RF63

Hi,

We are using the ADS54RF63 in combination with a Xilinx xc7k160tffg676-2 FPGA. The routes on the board are 100 Ohm differential and the termination resistor in the FPGA are on. Nevertheless we see reflections on the ADC outputs . Measuring the time until the reflection returns and calculating the distance with the correct propagation speed corresponds with the distance of the signal from the ADC to the FPGA which is around 80mm. We verified our measuring equipment with a ADS54RF63EVM mounted on a TSW1400. The signals on these boards are significant better. Do anyone have any ideas? Maybe someone are aware off problems with Xilinx FPGAs or have any recommendations. We tried to do some SI simulation, but our ECAD is to crappy to do this correct.

  • 0
    TI__Mastermind 29220 points

    Hi,

    If the scope and probe you are using have sufficient bandwidth to get a good look at the reflections then besides calculating the distance to the reflection you can use the amplitude of the reflection to calculate the amount of discontinuity at the reflection point.  The termination resistors in the FPGA will naturally have some tolerance to them about the nominal 100 ohms, or the parasitic capacitance at the inputs could be lowering the effective termination resistance for very sharp edged signals.   If the reflections are very bad it may turn out that the calculation of the discontinuity could lead to the conclusion that the termination resistors are not really enabled as believed, for some reason.   Adding a 100 ohm termination across the LVDS drivers at the ADC could terminate the reflections at the source so that the reflection can only make one round trip, but at the expense of reducing the signal swing.   Or, taking one of the boards without the FPGA installed you could install a 100 ohm resistor across the FPGA pads and then compare the reflections.  It could also be that the circuit board did not really hit the 100 ohm design goal - I have had that happen if the board shop quoted one stackup but built to another.

    Regards,

    Richard P.

  • 0 in reply to Richard Prentice
    Prodigy 40 points
    Hi Richard,

    Thanks for all the inputs. Unfortunately we already checked nearly everything you mentioned. The layer stackup should be fine as we tested the board to be compliant to USB3.0 and DisplayPort with an external laboratory. And these frequencies are much higher. Disabling the termination inside the FPGA destroys the signal totally. Also adding an external termination besides the disabled one doesn't improve the signal.
    The amplitude of the reflected signal is around 25%. If I calculated correct this should be 60 Ohm instead of 100. I have no idea how this can happen.

    I hopped you can point me to a commonly known issue with Xilinx FPGAs :-)

    Regards,
    Christian
  • 0 in reply to user4946482
    TI__Mastermind 29220 points

    hi,

    i am not aware on an issue with commonly available FPGAs where the termiantion resistors would be off by such a large amount.  Your experiment with external termination with the internal termination disabled is what i would have done.  The only other thing i could think of would be to also power down the FPGA to see if the signal cleans up with the FPGA powered down.   Or to try to isolate whether board routing is causing coupling between signals.  Maybe open up all the LVDS pairs at the source except for one left toggling at the FPGA and see if there is any change.

    Regards,

    Richard P.