ADS1198: Timing questions from datasheet

We have started using ADS1194 with 3.3v DVDD and internal 2.048 MHz clock.
In all my questions I am referring to ADS1198 datasheet with headline, page/figure numbers.

Q1- P.12 Fig.1
My understanding from this figure is

If controller is going to output data,DIN will be drived by controller tDIST before SCLK falling edge, and stays tDIHD after SCLK falling edge. DIN is latched by ADS on SCLK falling edge.
If controller is going to input data(upon seeing DRDY activated), Controller activates CS, waits at least tCSSC, then issues SCLK,
then DOUT will be drived by ADS at least tCSDOD seconds after CS goes low, OR It will be drived upon SCLK rising edge? Which one?

Q2- P.26 SCLK
"tSCLK < (tDR – 4tCLK)/(NBITS × NCHANNELS + 24)
For example, if the ADS1198 is used in a 500SPS mode the minimum SCLK speed is 80kHz."

But with 2.048MHz CLK and 500SPS, tDR=2ms and 4tCLK=1.96us, so tSCLK<2ms/152 or  SCLK>13.15KHz! How 80KHz is calculated?

Q3- P.28 Data Ready
Does /DRDY goes high on Falling edge of SCLK or Rising edge?
"Regardless of the status of the CS signal, a rising edge on SCLK pulls DRDY high."
but then 5 lines below:
"DRDY is pulled high at the falling edge of SCLK."

which one is correct?

Thanks.