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ADS1198: Behavior questions

Arash_
Prodigy 230 points

Part Number: ADS1198
Other Parts Discussed in Thread: ADS1194,

We have started using ADS1194 with 3.3v DVDD and internal 2.048 MHz clock.
In all my questions I am referring to ADS1198 datasheet with headline, page/figure numbers.

Q1-P.27 fig.28
"In read data continuous mode , the DOUT output line also indicates when new data are available. This feature can be used to minimize the number of connections between the device and the system controller."
Does this mean we don't need to monitor DRDY? Please explain the behavior of DOUT.

Q2- P.36 RDATAC
In Figure 38,

CS is not de-activated after the frist data is sent, should we keep CS active all the itme or only when we have a SPI transaction??
Why DOUT goes high for tUPDATE after frist data is sent? What is that glitch?


Q3- P.30 Fig.33
Please explain figure 33,


Why when Start pin goes low, DRDY is activated after tSDSU??? Shouldn't de-activate because conversion is stopped?
Why when START deactivates, DRDY is still active??

  • 0
    TI__Mastermind 38745 points
    Hello Arash,

    1. This only happens if CS is held low constantly. In this case you hold CS low in hardware and then you can monitor the DOUT line for a high to low transition to indicate new data so DRDY can be ignored. However, most processors probably cannot do this so you will need an FPGA to take advantage of this behavior.

    2. This diagram is kind of confusing because it is meant to be a generic diagram that shows the behavior in the case where you monitor DRDY for new data but also diagrams the functionality where you only monitor DOUT for new data as in question 1. DOUT will transition low to high just like DRDY if CS is low when new data are ready. Hopefully you would never observe this behavior in your end product because you will have written the code such that you always finish reading the last sample before a new one is ready.

    3. If the START pin is pulled low or the STOP command is given in between conversions, the current conversion will complete. That diagram is showing the "keep out" time around the DRDY falling edge relating to that behavior.

    Regards,
    Brian Pisani
  • 0 in reply to Brian Pisani
    Prodigy 230 points
    Hello Brian,
    Thanks so much for the answers. 2 confusions:
    1- CS should be active only during the SPI transaction(reading data/sending command), and it should become deactive when we're done with the SPI transaction. Is this right?
    In RDATAContinuos mode, the CS should be kept active all the time, or should become deactive after 152 bits are received?
    In other scenario, after we send cmd to ADS, should I deactivate CS?

    2- When START goes low, we won't have any data to send, so DRDY should be high(deactive). Correct?
  • 0 in reply to Arash_
    TI__Mastermind 38745 points

    Arash,

    1. What this is saying is that if there are no more slaves on the SPI bus, you can just tie CS low all the time. You don't "need" to bring it high for the chip to work.
    2. I think it will be low. Like I mentioned, the ADS1198 will complete any ongoing conversions when START is taken low. So if you take START low during a conversion, DRDY will remain high until the conversion completes, then it will go low. It will stay low until the next SCLK falling edge.

    Brian