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ADS1198: Settling time confusion

Arash_
Prodigy 230 points
Part Number: ADS1198


Q1-Is settling time required "only once" at the beginning when START is activated? Is tSETTLE=3xtDR or it's from Table 7? These 2 don't match.

Q2-In ADS1198 datasheet P.29 under Settling Time it says:

"Note that when START is held high and there is a step change in the input signal, it takes 3 × tDR for the filter to settle to the new value. Settled data are available on the fourth DRDY pulse."
What does it mean by fourth DRDY pulse?? Please explain.


Q3-Is the timing on Figure 31. correct?


Data is ready every tSettlingTime=3xtDR, so DRDY should go low every tSettlingTime=3xtDR because it takes tSETTLE for any conversion to settle?

  • 0
    TI__Mastermind 38745 points

    Hello Arash,

    1. The chip actually waits 4 cycles to output the data. The datasheet alludes to this, albeit in a cryptic way: "Settled data are available on the fourth nDRDY pulse." The times in table 7 are 4xt_dr + some extra time at the beginning.
    2. This is also kind of confusing language. It it referring to the low pass characteristics of the digital filter on the ADS1198. By "step change" it is referring literally to a unit step like you studied in college. If you were to apply a "unit step" to the input of the digital filter on the ADS1198, it would take 3 full conversion cycles to fully settle to 1. But of course all low pass filters will have some settling time so this should not be surprising. When it says you have to wait until the 4th, it is really saying that if you were to apply the step in between samples, you would have to wait until the 4th sample after that point to see the settled data because you can only read data every t_dr. Long story short, you should not need to worry about this behavior. This is much more important for a data converter that muxes between inputs.
    3. The diagram is correct. The device waits for the filter to settle before asserting DRDY.

    Brian

  • 0 in reply to Brian Pisani
    Prodigy 230 points
    Hi Brian,
    1- I am confused, 4 cycles of data rate? if it takes each output 4xt_dr to appear, the data rate is not t_dr, it's 0.25t_dr. Please advise.
    3- Diagram 31., is it valid for any input conversion or only when there is unit step inputs? If we don't have unit step inputs, chip outputs every t_dr?

    Thank you.
  • 0 in reply to Arash_
    TI__Mastermind 38745 points

    Hello Arash,

    1. Only for the first sample will the ADS1198 wait 4xt_dr to toggle DRDY. After that, when the device is running continuously and the START pin is either held high or the START command has been issued, the DRDY signal will assert at the data rate. I think your confusion may stem from past experience with SAR ADCs in which conversions are controlled ad hoc by the host. The ADS1198 is a delta-sigma ADC where the conversions happen continuously.

    3. That diagram is only valid for the first conversion after START is brought high or the START command is issued. See my response to question 1.

    Brian

  • 0 in reply to Brian Pisani
    Prodigy 230 points
    Thank you very much!